Patents by Inventor Naoyuki Shigyo
Naoyuki Shigyo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8533549Abstract: A memory system includes: a memory chip group including n chips of a nonvolatile semiconductor memory dividedly managed for each of unit areas having predetermined sizes, an unit area of one chip among the n chips storing an error correction code for a group including unit areas in the other n?1 chips associated with the unit area, and the chip that stores the error correction code being different for each of positions of the unit areas; and an access-destination calculating unit that designates, when data in the unit areas is rewritten, the unit area in which the error correction code of data is stored as a writing destination of rewriting data, and designates an unit area in which data before rewriting is stored as a storage destination of a new error correction code.Type: GrantFiled: February 1, 2010Date of Patent: September 10, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Shigeo Kondo, Kiyomi Naruke, Naoyuki Shigyo
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Patent number: 8503245Abstract: A non-volatile semiconductor memory device according to one aspect of an embodiment of the present invention includes: a semiconductor substrate; an element region; a plurality of memory cell transistors which each include a control gate electrode; and programming means for programming data to a programming target memory cell transistor by applying a programming voltage to the programming target memory cell transistor. Moreover, the programming means applies a programming voltage incremented stepwise from an initial programming voltage, to the programming target memory cell transistor while applying a constant initial intermediate voltage to memory cell transistors adjacent to the programming target memory cell transistor.Type: GrantFiled: March 4, 2011Date of Patent: August 6, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kunihiro Yamada, Naoyuki Shigyo, Michiru Hogyoku, Hideto Horii
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Patent number: 8369152Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cells without a source region and a drain region, and a first insulating film. The memory cells are arranged adjacent to one another on the semiconductor substrate and include a first gate electrode including a charge accumulation layer. A current path functioning as a source region or a drain region of a selected memory cell is formed in the semiconductor substrate when a voltage is applied to the first gate electrode of one of unselected memory cells. The first insulating film is formed on the semiconductor substrate to fill a region between the first gate electrodes of the memory cells adjacent to each other.Type: GrantFiled: June 17, 2010Date of Patent: February 5, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Shimane, Naoyuki Shigyo, Mutsuo Morikado
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Publication number: 20110228610Abstract: A non-volatile semiconductor memory device according to one aspect of an embodiment of the present invention includes: a semiconductor substrate; an element region; a plurality of memory cell transistors which each include a control gate electrode; and programming means for programming data to a programming target memory cell transistor by applying a programming voltage to the programming target memory cell transistor. Moreover, the programming means applies a programming voltage incremented stepwise from an initial programming voltage, to the programming target memory cell transistor while applying a constant initial intermediate voltage to memory cell transistors adjacent to the programming target memory cell transistor.Type: ApplicationFiled: March 4, 2011Publication date: September 22, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Kunihiro Yamada, Naoyuki Shigyo, Michiru Hogyoku, Hideto Horii
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Patent number: 7999324Abstract: A semiconductor device includes first, second, third, and fourth semiconductor regions, a gate electrode, and silicide layers. The first, second, and third semiconductor regions are formed in a semiconductor substrate while being spaced part from each other. The fourth semiconductor region is formed in the semiconductor substrate between the second semiconductor region and the third semiconductor region and has an electric resistance higher than the first, second, and third semiconductor regions. In a direction perpendicular to a direction to connect the first and second semiconductor regions, the fourth semiconductor region has a width smaller than that of the semiconductor substrate sandwiched between the first semiconductor region and the second semiconductor region. The gate electrode is formed above the semiconductor substrate between the first semiconductor region and the second semiconductor region.Type: GrantFiled: November 30, 2005Date of Patent: August 16, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Naoyuki Shigyo, Kentaro Watanabe
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Publication number: 20100329026Abstract: According to one embodiment, a semiconductor memory device includes memory cells, first and second selection transistors, a source line, a temperature monitor, and a source line voltage controller. The memory cells are connected in series between a source of the first selection transistor and a drain of the second selection transistor. The temperature monitor monitors a temperature of the semiconductor substrate. The source line voltage controller applies a voltage to the source line, in a read operation, in such a manner that a potential difference between the source line and the semiconductor substrate increases according to a rise in the temperature monitored by the temperature monitor and that a reverse bias is applied between the source of the second selection transistor and the semiconductor substrate.Type: ApplicationFiled: June 24, 2010Publication date: December 30, 2010Inventors: Mitsutoshi NAKAMURA, Takeshi Shimane, Michiru Hogyoku, Katsuaki Isobe, Naoyuki Shigyo
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Publication number: 20100322009Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cells without a source region and a drain region, and a first insulating film. The memory cells are arranged adjacent to one another on the semiconductor substrate and include a first gate electrode including a charge accumulation layer. A current path functioning as a source region or a drain region of a selected memory cell is formed in the semiconductor substrate when a voltage is applied to the first gate electrode of one of unselected memory cells. The first insulating film is formed on the semiconductor substrate to fill a region between the first gate electrodes of the memory cells adjacent to each other.Type: ApplicationFiled: June 17, 2010Publication date: December 23, 2010Inventors: Takeshi SHIMANE, Naoyuki Shigyo, Mutsuo Morikado
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Publication number: 20100313101Abstract: A memory system includes: a memory chip group including n chips of a nonvolatile semiconductor memory dividedly managed for each of unit areas having predetermined sizes, an unit area of one chip among the n chips storing an error correction code for a group including unit areas in the other n?1 chips associated with the unit area, and the chip that stores the error correction code being different for each of positions of the unit areas; and an access-destination calculating unit that designates, when data in the unit areas is rewritten, the unit area in which the error correction code of data is stored as a writing destination of rewriting data, and designates an unit area in which data before rewriting is stored as a storage destination of a new error correction code.Type: ApplicationFiled: February 1, 2010Publication date: December 9, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shigeo Kondo, Kiyomi Naruke, Naoyuki Shigyo
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Patent number: 7823114Abstract: A method of designing a wiring structure of an LSI is capable of reducing a capacitance variation ratio ?C/C or a resistance-by-capacitance variation ratio ?(RC)/(RC) of the wiring structure.Type: GrantFiled: April 16, 2008Date of Patent: October 26, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Naoyuki Shigyo, Tetsuya Yamaguchi
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Publication number: 20080201682Abstract: A method of designing a wiring structure of an LSI is capable of reducing a capacitance variation ratio ?C/C or a resistance-by-capacitance variation ratio ?(RC)/(RC) of the wiring structure.Type: ApplicationFiled: April 16, 2008Publication date: August 21, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Naoyuki Shigyo, Tetsuya Yamaguchi
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Patent number: 7373627Abstract: A method of designing a wiring structure of an LSI is capable of reducing a capacitance variation ratio ?C/C or a resistance-by-capacitance variation ratio ?(RC)/(RC) of the wiring structure.Type: GrantFiled: October 6, 2005Date of Patent: May 13, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Naoyuki Shigyo, Tetsuya Yamaguchi
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Publication number: 20060125023Abstract: A semiconductor device includes first, second, third, and fourth semiconductor regions, a gate electrode, and silicide layers. The first, second, and third semiconductor regions are formed in a semiconductor substrate while being spaced part from each other. The fourth semiconductor region is formed in the semiconductor substrate between the second semiconductor region and the third semiconductor region and has an electric resistance higher than the first, second, and third semiconductor regions. In a direction perpendicular to a direction to connect the first and second semiconductor regions, the fourth semiconductor region has a width smaller than that of the semiconductor substrate sandwiched between the first semiconductor region and the second semiconductor region. The gate electrode is formed above the semiconductor substrate between the first semiconductor region and the second semiconductor region.Type: ApplicationFiled: November 30, 2005Publication date: June 15, 2006Inventors: Naoyuki Shigyo, Kentaro Watanabe
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Publication number: 20060059445Abstract: A method of designing a wiring structure of an LSI is capable of reducing a capacitance variation ratio ?C/C or a resistance-by-capacitance variation ratio ?(RC)/(RC) of the wiring structure.Type: ApplicationFiled: October 6, 2005Publication date: March 16, 2006Applicant: Kabushiki Kaisha ToshibaInventors: Naoyuki Shigyo, Tetsuya Yamaguchi
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Patent number: 6978434Abstract: A wiring structure of a semiconductor device, includes a wiring layer formed on an insulating film, a width (W) of each wire in the wiring layer and a thickness (H) of the insulating film satisfying “W/H<1” a length (L) of each wiring in the wiring layer being equal to or longer than 1 mm.Type: GrantFiled: June 23, 2000Date of Patent: December 20, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Naoyuki Shigyo, Tetsuya Yamaguchi
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Patent number: 6956747Abstract: There is disclosed a semiconductor device comprising at least one first pad being formed above a substrate and given a first potential, at least one first conductive layer being formed between the first pad and the substrate so as to be electrically connected to the first pad, at least one second pad being formed above the substrate so as to sandwich the at least one first conductive layer between the second pad and the substrate, and given a second potential different from the first potential, at least one second conductive layer being formed between the first and second pads and the substrate so as to be electrically connected to the second pad, and a plurality of insulating layers being stacked on the substrate and at least one of the insulating layers being as an inter-electrode insulator of a capacitance element.Type: GrantFiled: February 4, 2005Date of Patent: October 18, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Naoyuki Shigyo, Takayuki Hiraoka, Kentaro Watanabe
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Publication number: 20030081363Abstract: An ESD protection device comprising a field-effect transistor which including a source/drain diffusion layer formed in a semiconductor region, a gate insulating film formed on a channel region between the source/drain diffusion layers, and a gate electrode formed on the gate insulating film. The first silicide layer formed on a region of one portion of the source/drain diffusion layer. A diffusion layer formed in the semiconductor region of a non-forming region of the first silicide layer in the source/drain diffusion layer. A junction depth of the diffusion layer is smaller than that of the source/drain diffusion layer.Type: ApplicationFiled: October 24, 2002Publication date: May 1, 2003Inventors: Hirobumi Kawashima, Naoyuki Shigyo, Seiji Yasuda
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Patent number: 6222224Abstract: A nonvolatile semiconductor memory has memory cells (1) each having an insulated-gate FET that has an information storage part. A semiconductor region (27) is formed at the surface of a channel region of each memory cell. The semiconductor region has the same conductivity type as a channel conductivity type and functions to decrease the strength of an electric field at the surface of the channel region. If the insulated-gate FET is of an n-channel type, the semiconductor region is of an n-type. The semiconductor region suppresses threshold voltage variations among the insulated-gate FETs of the memory cells and prevents soft-writing in the memory cells.Type: GrantFiled: December 19, 1997Date of Patent: April 24, 2001Assignee: Kabushiki Kaisha ToshibaInventor: Naoyuki Shigyo
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Patent number: 6195790Abstract: A &Dgr;Z calculator calculates difference between an inversion layer capacitance by a classical theory and an inversion layer capacitance by a quantum theory, calculates &Dgr;Z which is a thickness of a semiconductor substrate equivalent to the difference in inversion layer capacitance. A discretization mesh generator generates a Delaunay discretization mesh for a structure of the semiconductor device to be evaluated. An electrical parameter calculator calculates electrical parameters of the semiconductor device under constraint that a charge density of channel conductivity type of the semiconductor device is set to zero at discretization mesh points of the discretization mesh on an interface between an insulating film and the semiconductor substrate and at discretization mesh points of the discretization mesh in the semiconductor substrate which are located within a distance less than the stored &Dgr;Z from the interface between the insulating film and the semiconductor substrate.Type: GrantFiled: April 17, 1998Date of Patent: February 27, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyoshi Tanimoto, Toshiyuki Enda, Naoyuki Shigyo, Kazuya Matsuzawa
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Patent number: 6051452Abstract: A silicon oxide layer serving as an insulation layer is formed on a p-type semiconductor substrate. An n.sup.+ -type source and drain regions are formed on the p-type substrate 110 with a spacing therebetween. A channel region is interposed between the source and drain regions. A silicon oxide layer serving as an insulation layer is formed on the channel region. A gate terminal is formed on the silicon oxide layer. High-concentration p-type regions are formed in the p-type semiconductor substrate under the source and drain regions, respectively.Type: GrantFiled: January 6, 1998Date of Patent: April 18, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Naoyuki Shigyo, Toshiyuki Enda
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Patent number: 5760442Abstract: A first silicon oxide layer serving as an insulation layer is formed on a p-type semiconductor substrate. An n.sup.+ -type source and drain regions are formed on the p-type substrate 110 with a spacing therebetween. A channel region is interposed between the source and drain regions. A second silicon oxide layer serving as a gate insulation layer is formed on the channel region. A gate terminal is formed on the second silicon oxide layer. High-concentration p-type regions are formed in the p-type semiconductor substrate under the source and drain regions, respectively.Type: GrantFiled: September 29, 1995Date of Patent: June 2, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Naoyuki Shigyo, Toshiyuki Enda