Patents by Inventor Naoyuki Takeda

Naoyuki Takeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230268398
    Abstract: In an RFC diode, a semiconductor substrate includes an n? drift layer, an n buffer layer, and a diffusion layer provided between and in contact with the n buffer layer and a second metal layer. The diffusion layer includes an n+ cathode layer provided in contact with the n buffer layer and the second metal layer in a diode region. The n+ cathode layer includes a first n+ cathode layer in contact with the second metal layer and a second n+ cathode layer provided between the first n+ cathode layer and the n buffer layer in contact with the n buffer layer. Crystal defect density of the first n+ cathode layer is higher than crystal defect density of another diffusion layer.
    Type: Application
    Filed: December 6, 2022
    Publication date: August 24, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventors: Katsumi NAKAMURA, Naoyuki TAKEDA, Mikihito SUZUKI, Koji TANAKA
  • Publication number: 20230131163
    Abstract: A semiconductor device includes a first electrode and a second electrode. The first electrode is connected to a collector layer and a first portion on the collector layer side of a cathode layer. The second electrode is connected to a second portion of the cathode layer excluding the first portion. A work function of the first electrode is larger than a work function of the second electrode, and one of the first electrode and the second electrode and the semiconductor substrate sandwich another of the first electrode and the second electrode in a thickness direction of the semiconductor substrate.
    Type: Application
    Filed: August 15, 2022
    Publication date: April 27, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventors: Koichi NISHI, Koji TANAKA, Shinya SONEDA, Shigeto HONDA, Naoyuki TAKEDA
  • Publication number: 20230056433
    Abstract: Provided are a time series data management unit that manages time series data generated in a target system, and a context management unit that manages a context registered by a user in association with time series data managed by a time series data management unit. The context management unit executes a process of extracting time series data associated with a context set as a search target by the user out of the managed time series data.
    Type: Application
    Filed: June 21, 2022
    Publication date: February 23, 2023
    Inventors: Yoshinori MOCHIZUKI, Naoyuki TAKEDA, Daisuke INABA
  • Publication number: 20220367222
    Abstract: In a wafer hand, two carry portions are arranged in line in a first direction, the two carry portions are connected via a joint portion, each of the two carry portions extends from the joint portion in a second direction orthogonal to the first direction, an interval between inner side surfaces of the two carry portions is 170 mm or more, an interval between outer side surfaces of the two carry portions is 280 mm or less, and when a distance between inner side surfaces of the two carry portions is A (mm), and a length of the inner side surfaces of the two carry portions in the second direction is L (mm), a relationship of L?(3002?A2)0.5 is satisfied.
    Type: Application
    Filed: March 3, 2022
    Publication date: November 17, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Naoyuki TAKEDA, Hiroshi TANAKA
  • Patent number: 11101150
    Abstract: A wafer grinding apparatus performs grinding processing for grinding a semiconductor wafer with a grindstone. The grindstone has a wear rate as a characteristic. The wear rate is 5% or more, and less than 200%. A determination part performs determination processing for determining whether a grinding state with respect to the semiconductor wafer is abnormal or normal, based on at least one of a load current of a motor and a grinding wear amount.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: August 24, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naoyuki Takeda, Kazunari Nakata
  • Patent number: 10649338
    Abstract: The present invention has an object of providing a stepped wafer that can prevent a resist from remaining after development, and a method for manufacturing the stepped wafer. The stepped wafer according to the present invention is a stepped wafer having a step and whose main surface is thinner in a center portion and is thicker in an outer periphery. The step includes a curved surface with a radius of curvature ranging from 300 ?m to 1800 ?m.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: May 12, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Naoyuki Takeda
  • Publication number: 20190355596
    Abstract: A wafer grinding apparatus performs grinding processing for grinding a semiconductor wafer with a grindstone. The grindstone has a wear rate as a characteristic. The wear rate is 5% or more, and less than 200%. A determination part performs determination processing for determining whether a grinding state with respect to the semiconductor wafer is abnormal or normal, based on at least one of a load current of a motor and a grinding wear amount.
    Type: Application
    Filed: April 2, 2019
    Publication date: November 21, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Naoyuki TAKEDA, Kazunari NAKATA
  • Patent number: 10073360
    Abstract: An edge exposure apparatus for exposure of an outer circumferential portion of a semiconductor substrate to light includes a light source provided to be able to emit light to the outer circumferential portion and a mirror having a reflection surface arranged to extend in a direction intersecting with an optical axis of light emitted from the light source. The mirror is provided between the outer circumferential portion and a center of the semiconductor substrate in a radial direction of the semiconductor substrate in exposure of the outer circumferential portion of the semiconductor substrate to light.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: September 11, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naoyuki Takeda, Shoichi Kuga
  • Publication number: 20180136560
    Abstract: The present invention has an object of providing a stepped wafer that can prevent a resist from remaining after development, and a method for manufacturing the stepped wafer. The stepped wafer according to the present invention is a stepped wafer having a step and whose main surface is thinner in a center portion and is thicker in an outer periphery. The step includes a curved surface with a radius of curvature ranging from 300 ?m to 1800 ?m.
    Type: Application
    Filed: July 8, 2015
    Publication date: May 17, 2018
    Applicant: Mitsubishi Electric Corporation
    Inventor: Naoyuki TAKEDA
  • Publication number: 20180024437
    Abstract: An edge exposure apparatus for exposure of an outer circumferential portion of a semiconductor substrate to light includes a light source provided to be able to emit light to the outer circumferential portion and a mirror having a reflection surface arranged to extend in a direction intersecting with an optical axis of light emitted from the light source. The mirror is provided between the outer circumferential portion and a center of the semiconductor substrate in a radial direction of the semiconductor substrate in exposure of the outer circumferential portion of the semiconductor substrate to light.
    Type: Application
    Filed: January 28, 2015
    Publication date: January 25, 2018
    Applicant: Mitsubishi Electric Corporation
    Inventors: Naoyuki TAKEDA, Shoichi KUGA
  • Patent number: 5594922
    Abstract: A plurality of higher-level units are connected to a library unit, for example, as a lower-level unit through an SCSI. Furthermore, the plurality of higher-level units are connected by means of a communication path to mutually exchange information regarding the status of use of SCSI for the access to the lower-level library unit. A monitoring control section is provided in each of the plurality of higher-level units to instruct necessary processing in response to the status of use of SCSI. Particularly, when an abnormal occupation of SCSI caused by hang-up of any other higher-level unit is detected by the monitoring control section of a higher-level unit, the higher-level unit instructs its own SCSI controller to reset the bus to achieve bus reset of the other SCSI controller, thus releasing the occupation.
    Type: Grant
    Filed: September 6, 1994
    Date of Patent: January 14, 1997
    Assignee: Fujitsu Limited
    Inventors: Yoshio Suzuki, Naoyuki Takeda