Patents by Inventor Naoyuki Takeshita
Naoyuki Takeshita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240070468Abstract: Transfer learning for a target domain that partially matches classification of a source domain having a ground truth is enabled. A learning device stores a first set subjected to classification and assigned with a ground truth and a second set having a class that partially matches the first set, and executes, based on a first loss function of first data and a second loss function of second data, processing of updating, by the number of updates, an identifier for identifying the first data and the second data when a feature of the first data or a feature of the second data is input. The learning device calculates a similarity at which the first data is similar to the second data by a data selector that calculates the similarity at the last time, and updates the data selector and the first distribution based on the estimated value.Type: ApplicationFiled: July 17, 2023Publication date: February 29, 2024Inventors: Koki TAKESHITA, Naoyuki TERASHITA
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Patent number: 11241945Abstract: A molding configured not to be misaligned with a predetermined mounting position provides a vehicle with good appearance, avoids in advance interference with other parts when a door is opened or closed, and reduces wind noise while the vehicle is running. An end cap having a locking part is crimped to a rear end of a molding. An upper glass run has, at its rear end, an insertion slot into which the locking part is inserted. The locking part is inserted in the insertion slot and locked to the rear end of the upper glass run.Type: GrantFiled: November 30, 2018Date of Patent: February 8, 2022Assignees: Nishikawa Rubber Co., Ltd., MAZDA MOTOR CORPORATIONInventors: Kazuyuki Takeda, Hirotaka Takaya, Kyohei Yukita, Naoyuki Takeshita, Shinsuke Hirao
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Patent number: 11042431Abstract: A failure prediction apparatus includes a memory and a processor coupled to the memory. The processor acquires a score based on an output of each of a plurality of sensors associated with each of a plurality of circuit arrangement regions, in each of the plurality of circuit arrangement regions a logic circuit constructed by programming is arrangeable, and performs a process of making a determination on a possibility of an occurrence of a failure with respect to each of the plurality of circuit arrangement regions based on the score for each of the circuit arrangement regions.Type: GrantFiled: April 23, 2019Date of Patent: June 22, 2021Assignee: FUJITSU LIMITEDInventors: Kunihiko Matsumoto, Naoyuki Takeshita, Masahiro Dohi, Hisaya Urabe
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Publication number: 20190354419Abstract: A failure prediction apparatus includes a memory and a processor coupled to the memory. The processor acquires a score based on an output of each of a plurality of sensors associated with each of a plurality of circuit arrangement regions, in each of the plurality of circuit arrangement regions a logic circuit constructed by programming is arrangeable, and performs a process of making a determination on a possibility of an occurrence of a failure with respect to each of the plurality of circuit arrangement regions based on the score for each of the circuit arrangement regions.Type: ApplicationFiled: April 23, 2019Publication date: November 21, 2019Applicant: FUJITSU LIMITEDInventors: Kunihiko Matsumoto, Naoyuki Takeshita, Masahiro Dohi, Hisaya Urabe
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Patent number: 9871624Abstract: A transmission apparatus includes a first storage configured to store data received from external into a write enable area, a second storage configured to store the data in accordance with a write request and output a retry request in response to occurring an error of writing a first data included in the data, and a controller configured to read the data from the first storage and send the write request to the second storage, set an area of the first storage storing the first data to a write disable area in combination with stop sending the retry request to external when receiving the retry request from the second storage, and send the first data reading from the write disable area of the first storage to external in response to a read request from external.Type: GrantFiled: August 23, 2016Date of Patent: January 16, 2018Assignee: FUJITSU LIMITEDInventors: Hiroaki Shiraishi, Tateo Shimaru, Naoyuki Takeshita, Katsuhiko Hirashima, Masaru Nishida, Tsuneharu Suzuki, Hisaya Urabe
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Publication number: 20170063496Abstract: A transmission apparatus includes a first storage configured to store data received from external into a write enable area, a second storage configured to store the data in accordance with a write request and output a retry request in response to occurring an error of writing a first data included in the data, and a controller configured to read the data from the first storage and send the write request to the second storage, set an area of the first storage storing the first data to a write disable area in combination with stop sending the retry request to external when receiving the retry request from the second storage, and send the first data reading from the write disable area of the first storage to external in response to a read request from external.Type: ApplicationFiled: August 23, 2016Publication date: March 2, 2017Applicant: FUJITSU LIMITEDInventors: Hiroaki Shiraishi, Tateo Shimaru, Naoyuki Takeshita, Katsuhiko Hirashima, Masaru Nishida, Tsuneharu Suzuki, Hisaya Urabe
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Patent number: 8261162Abstract: A decoding device includes a first receiving section for receiving a data packets, a second receiving section for receiving a plurality of error correction packets which includes matrix configuration information regarding the plural data packets, a deciding section for deciding a number of packets to be accumulated to restore a lost data packet, based on the matrix configuration information, an accumulating section for accumulating the data packets received by the first receiving section in the number of packets to be accumulated, and a restoring section for, when a loss of any of the data packets received by the first receiving section is detected, restoring the lost data packet by using at least one of the data packets and the error correction packets.Type: GrantFiled: March 25, 2010Date of Patent: September 4, 2012Assignee: Fujitsu LimitedInventors: Kazumi Doi, Jun Endoh, Masahiro Abe, Naoyuki Takeshita, Takafumi Kamito, Koichi Onimaru, Yasutaka Umemoto, Noriyuki Ihara
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Patent number: 8094160Abstract: A moving-picture processing apparatus has a pre-fetch memory pre-fetching a portion of a decoded picture stored in an external memory, and a miss/hit determination unit determining a manner in which a miss occurs in response to a read request to the pre-fetch memory.Type: GrantFiled: September 4, 2007Date of Patent: January 10, 2012Assignee: Fujitsu LimitedInventors: Yasuhiro Watanabe, Mitsuharu Wakayoshi, Naoyuki Takeshita
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Patent number: 8036266Abstract: Each of a plurality of encoders calculates a first time by adding an encoding delay time commonly determined between the encoders to a value of an STC counter, and transmits a system stream generated by including the calculated first time to a decoder associated with the encoder in one-to-one correspondence, of a plurality of decoders constituting a decoding system. Each of the decoders calculates a second time by adding the first time to an estimated maximum value commonly determined between the decoders by adding a decoding delay time to a value of stream fluctuation of an output time occurring between the encoders, and outputs the divided image data decoded from the system stream to a synthesizer that synthesizes the image data at the calculated second time.Type: GrantFiled: October 23, 2007Date of Patent: October 11, 2011Assignee: Fujitsu LimitedInventors: Naoshi Kayashima, Takato Ohashi, Hiroshi Ohtsuru, Naoyuki Takeshita, Kazuhiro Yamashita, Yousuke Yamaguchi, Atsushi Ichiki, Shin Fujita
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Publication number: 20100251060Abstract: A decoding device includes a first receiving section for receiving a data packets, a second receiving section for receiving a plurality of error correction packets which includes matrix configuration information regarding the plural data packets, a deciding section for deciding a number of packets to be accumulated to restore a lost data packet, based on the matrix configuration information, an accumulating section for accumulating the data packets received by the first receiving section in the number of packets to be accumulated, and a restoring section for, when a loss of any of the data packets received by the first receiving section is detected, restoring the lost data packet by using at least one of the data packets and the error correction packets.Type: ApplicationFiled: March 25, 2010Publication date: September 30, 2010Applicant: FUJITSU LIMITEDInventors: Kazumi DOI, Jun Endoh, Masahiro Abe, Naoyuki Takeshita, Takafumi Kamito, Koichi Onimaru, Yasutaka Umemoto, Noriyuki Ihara
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Patent number: 7466967Abstract: A communication system that can improve communication quality by accurately re-creating reproduction timing at the receiving end even at the time of receiving VBR data or in the case of the occurrence of a packet loss. A send rate recognition section recognizes a send rate from a time stamp. A memory stores data. A dummy data addition section adds dummy data for correcting the difference between a read rate set for reading out data from the memory and the send rate to the data written to the memory. A read clock generation section generates a read clock which is equal to the read rate. A dummy data removal section removes the dummy data from the data read out from the memory on the basis of the read clock.Type: GrantFiled: November 8, 2005Date of Patent: December 16, 2008Assignee: Fujitsu LimitedInventors: Naoyuki Takeshita, Toshikazu Senuki, Tetsuya Yasui, Shinichirou Miyajima, Yuji Ishii, Katsuhiro Eguchi, Masahiro Abe, Jun Endoh
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Publication number: 20080152020Abstract: Each of a plurality of encoders calculates a first time by adding an encoding delay time commonly determined between the encoders to a value of an STC counter, and transmits a system stream generated by including the calculated first time to a decoder associated with the encoder in one-to-one correspondence, of a plurality of decoders constituting a decoding system. Each of the decoders calculates a second time by adding the first time to an estimated maximum value commonly determined between the decoders by adding a decoding delay time to a value of stream fluctuation of an output time occurring between the encoders, and outputs the divided image data decoded from the system stream to a synthesizer that synthesizes the image data at the calculated second time.Type: ApplicationFiled: October 23, 2007Publication date: June 26, 2008Applicant: FUJITSU LIMITEDInventors: Naoshi Kayashima, Takato Ohashi, Hiroshi Ohtsuru, Naoyuki Takeshita, Kazuhiro Yamashita, Yousuke Yamaguchi, Atsushi Ichiki, Shin Fujita
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Publication number: 20080059716Abstract: A moving-picture processing apparatus has a pre-fetch memory pre-fetching a portion of a decoded picture stored in an external memory, and a miss/hit determination unit determining a manner in which a miss occurs in response to a read request to the pre-fetch memory.Type: ApplicationFiled: September 4, 2007Publication date: March 6, 2008Applicant: Fujitsu LimitedInventors: Yasuhiro Watanabe, Mitsuharu Wakayoshi, Naoyuki Takeshita
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Patent number: 7280507Abstract: If a radio LAN apparatus moves from a communication range of a first access point to a communication range of a second access point, and if communication link between the radio LAN apparatus and the first access point is broken, a memory control section stops transmitting data to the first access point. At this time, data to be transmitted to the first access point are not deleted from memory. After the radio LAN apparatus enters the communication range of the second access point, the memory control section resumes transmission of the data stored in the memory. Thereafter, the next data are transmitted. Thus, the data is transmitted in proper sequence.Type: GrantFiled: February 19, 2004Date of Patent: October 9, 2007Assignee: Fujitsu LimitedInventors: Shinichirou Miyajima, Kazuhiro Ichiyanagi, Akiko Kusumoto, Yuji Nagano, Katsuhiro Eguchi, Naoyuki Takeshita, Yuji Ishii, Kazuyuki Inomoto
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Publication number: 20060056242Abstract: A communication system that can improve communication quality by accurately re-creating reproduction timing at the receiving end even at the time of receiving VBR data or in the case of the occurrence of a packet loss. A send rate recognition section recognizes a send rate from a time stamp. A memory stores data. A dummy data addition section adds dummy data for correcting the difference between a read rate set for reading out data from the memory and the send rate to the data written to the memory. A read clock generation section generates a read clock which is equal to the read rate. A dummy data removal section removes the dummy data from the data read out from the memory on the basis of the read clock.Type: ApplicationFiled: November 8, 2005Publication date: March 16, 2006Inventors: Naoyuki Takeshita, Toshikazu Senuki, Tetsuya Yasui, Shinichirou Miyajima, Yuji Ishii, Katsuhiro Eguchi, Masahiro Abe, Jun Endoh
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Publication number: 20050013265Abstract: If a radio LAN apparatus moves from a communication range of a first access point to a communication range of a second access point, and if communication link between the radio LAN apparatus and the first access point is broken, a memory control section stops transmitting data to the first access point. At this time, data to be transmitted to the first access point are not deleted from memory. After the radio LAN apparatus enters the communication range of the second access point, the memory control section resumes transmission of the data stored in the memory. Thereafter, the next data are transmitted. Thus, the data is transmitted in proper sequence.Type: ApplicationFiled: February 19, 2004Publication date: January 20, 2005Applicant: FUJITSU LIMITEDInventors: Shinichirou Miyajima, Kazuhiro Ichiyanagi, Akiko Kusumoto, Yuji Nagano, Katsuhiro Eguchi, Naoyuki Takeshita, Yuji Ishii, Kazuyuki Inomoto