Patents by Inventor Naoyuki Urasaki

Naoyuki Urasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090315049
    Abstract: An optical semiconductor element mounting package that has good adhesion between the resin molding and the lead electrodes and has excellent reliability is provided, as well as an optical semiconductor device using the package is also provided. The optical semiconductor element mounting package having a recessed part that serves as an optical semiconductor element mounting region, wherein the package is formed by integrating: a resin molding composed of a thermosetting light-reflecting resin composition, which forms at least the side faces of the recessed part; and at least a pair of positive and negative lead electrodes disposed opposite each other so as to form part of the bottom face of the recessed part, and there is no gap at a joint face between the resin molding and the lead electrodes.
    Type: Application
    Filed: May 21, 2007
    Publication date: December 24, 2009
    Inventors: Naoyuki Urasaki, Kanako Yuasa
  • Publication number: 20090095969
    Abstract: A substrate for mounting optical semiconductor elements is provided, including a base substrate having an insulating layer and a plurality of wiring circuits formed on the upper face of the insulating layer, and having at least one external connection terminal formation opening portion which penetrates the insulating layer and reaches the wiring circuits; and an optical reflection member, which is provided on the upper face of the base substrate, and which forms at least one depressed portion serving as an area for mounting an optical semiconductor element.
    Type: Application
    Filed: September 12, 2008
    Publication date: April 16, 2009
    Inventors: Hayato Kotani, Naoyuki Urasaki, Makoto Mizutani
  • Patent number: 6281450
    Abstract: A substrate for mounting a semiconductor chip having bumps using an adhesive thereon, said substrate being, for instance, provided with an insulating coating having an opening in the semiconductor chip mounting area so that the wiring conductors will not be exposed to the substrate surface near the boundary of the semiconductor chip mounting area, is improved in connection reliability and has high mass productivity.
    Type: Grant
    Filed: December 27, 1999
    Date of Patent: August 28, 2001
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Naoyuki Urasaki, Yasusi Simada, Yoshiyuki Tsuru, Akishi Nakaso, Itsuo Watanabe
  • Patent number: 6197149
    Abstract: An insulating varnish comprising a resin component, electrical insulating whiskers, and if necessary, one or more additives such as an ion adsorbent, and/or an organic reagent for preventing injury from copper, produced by adding the additives to the resin component and the whiskers, or filtering the whiskers, or milled by using a beads mill or a three-roll mill, or the like, is excellent for producing a multilayer printed circuit board having high wiring density, high reliability and excellent other electrical properties.
    Type: Grant
    Filed: April 9, 1998
    Date of Patent: March 6, 2001
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Kazuhito Kobayashi, Yasushi Kumashiro, Atsushi Takahashi, Koji Morita, Takahiro Tanabe, Kazunori Yamamoto, Akishi Nakaso, Shigeharu Arike, Kazuhisa Otsuka, Naoyuki Urasaki, Daisuke Fujimoto, Nozomu Takano
  • Patent number: 5879568
    Abstract: A multilayer printed circuit board small in interlayer thickness, capable of fine wiring, minimized in IVH and BVH diameters, high in strength and also excellent in wire bonding workability can be produced by a process comprising the steps of coating a thermosetting resin varnish compounded with electrically insulating whiskers on a roughened side of a copper foil, semi-curing the resin by heating to form a thermosetting resin layer, integrally laminating it on an interlayer board in which plated through-holes and conductor circudits have been formed, and roughening the cured thermosetting resin layer on the via hole wall surfaces with a roughening agent.
    Type: Grant
    Filed: June 6, 1997
    Date of Patent: March 9, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Naoyuki Urasaki, Kouichi Tsuyama, Kazuhito Kobayashi, Norio Okano, Hiroshi Shimizu, Nobuyuki Ogawa, Akishi Nakaso, Toyoki Ito, Daisuke Fujimoto, Kazuhisa Otsuka, Shigeharu Arike, Yoshiyuki Tsuru
  • Patent number: 5689879
    Abstract: A metal foil for printed wiring boards comprising a first copper layer to be adhered to a resin, a second copper layer having a sufficient strength as a metal layer and a nickel-phosphorus alloy layer containing 1.1% by weight or more of phosphorus formed between the first and second copper layers is suitable for producing printed wiring boards having excellent heat resistance, particularly during production procedures.
    Type: Grant
    Filed: December 16, 1994
    Date of Patent: November 25, 1997
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Naoyuki Urasaki, Kouichi Tsuyama, Kiyoshi Hasegawa, Shuichi Hatakeyama, Akinari Kida, Akishi Nakaso, Hiroshi Nomura
  • Patent number: 5638598
    Abstract: A process for producing a wiring board involves laminating a metal foil on both sides of an insulating substrate not completely cured, followed by pressing with heating; drilling holes in the resulting laminate for connecting circuits therein; removing portions of the metal foils in narrow areas around the holes to form hollow portions in the metal foils; and filling a flowable electroconductive substance in the holes and the hollow portions.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: June 17, 1997
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Akishi Nakaso, Kouichi Tsuyama, Akinari Kida, Shuichi Hatakeyama, Naoyuki Urasaki
  • Patent number: 5444189
    Abstract: A wiring board comprising one or more inner layer circuit substrates and outer circuit layers formed from metal foil layers on both sides of said dinner layer circuit substrates via prepregs, said inner layer circuit substrate comprising an insulating layer and metal foil layers formed on both sides of said insulating layer, at least one inner layer circuit substrate or said outer circuit layers or both having hollow portions in the metal foil layer filled with an electroconductive substance, said wiring board having one or more through-holes at least in the hollow portions and filled with the electroconductive substance, has high reliability and a high wiring density.
    Type: Grant
    Filed: June 17, 1993
    Date of Patent: August 22, 1995
    Assignee: Hitachi Chemical Co., Ltd.
    Inventors: Akishi Nakaso, Kouichi Tsuyama, Akinari Kida, Shuichi Hatakeyama, Naoyuki Urasaki
  • Patent number: 5403672
    Abstract: A metal foil for printed wiring boards comprising a first copper layer to be adhered to a resin, a second copper layer having a sufficient strength as a metal layer and a nickel-phosphorus alloy layer containing 1.1% by weight or more of phosphorus formed between the first and second copper layers is suitable for producing printed wiring boards having excellent heat resistance, particularly during production procedures.
    Type: Grant
    Filed: May 12, 1993
    Date of Patent: April 4, 1995
    Assignee: Hitachi Chemical Co., Ltd.
    Inventors: Naoyuki Urasaki, Kouichi Tsuyama, Kiyoshi Hasegawa, Shuichi Hatakeyama, Akinari Kida, Akishi Nakaso, Hiroshi Nomura