Abstract: A system receives assertions representing properties of a circuit design. The system determines a representation of an alternating Büchi automaton based on the assertions. The system transforms the representation of the alternating Büchi automaton to generate a representation of a simplified alternating Büchi automaton. The simplified alternating Büchi automaton has fewer states than the alternating Büchi automaton. One or more states of the simplified alternating Büchi automaton are obtained by merging states of the alternating Büchi automaton representing the assertions of the circuit. The system performs formal verification of the circuit design using the simplified alternating Büchi automaton.

Abstract: Forming a logic circuit design from a behavioral description language that includes N force and M release statements applied to a net disposed in the design, includes, in part, forming N multiplexers and a controller controlling the select terminals of the N multiplexers. Each multiplexer receives a force signal at its first input terminal. The output signal of the ith multiplexer is supplied to a second input terminal of (i+1)th multiplexer. A driver signal driving the net in the absence of the force statements is applied to a second input terminal of a first multiplexer. The controller asserts the select signal of the ith multiplexer if the ith force condition is active, and unasserts the select signal of the ith multiplexer if any one of a number of predefined conditions is satisfied.

Abstract: Forming a logic circuit design from a behavioral description language that includes N force and M release statements applied to a net disposed in the design, includes, in part, forming N multiplexers and a controller controlling the select terminals of the N multiplexers. Each multiplexer receives a force signal at its first input terminal. The output signal of the ith multiplexer is supplied to a second input terminal of (i+1)th multiplexer. A driver signal driving the net in the absence of the force statements is applied to a second input terminal of a first multiplexer. The controller asserts the select signal of the ith multiplexer if the ith force condition is active, and unasserts the select signal of the ith multiplexer if any one of a number of predefined conditions is satisfied.