Patents by Inventor Naping Kuo

Naping Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10795770
    Abstract: Methods, systems and apparatus including computer-readable mediums for rearranging data for refresh operations in memory systems such as NAND flash memory devices are provided. In one aspect, a method includes: determining that a particular logical page in a logical block fails based on error bits in a particular physical page that is in a first physical block mapped with the logical block and corresponds to the particular logical page, logical pages in the logical block being mapped to physical pages in the first physical block with an initial mapping order, and executing a refresh operation on the first physical block with a rearranged mapping order for the logical block, the rearranged mapping order being different from the initial mapping order. For the refresh operation, the logical pages in the logical block are mapped to physical pages in a second physical block with the rearranged mapping order.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: October 6, 2020
    Assignees: Macronix International Co., Ltd., MegaChips Corporation
    Inventors: Yuchih Yeh, Naping Kuo, Yuko Tamagawa
  • Publication number: 20190324855
    Abstract: Methods, systems and apparatus including computer-readable mediums for rearranging data for refresh operations in memory systems such as NAND flash memory devices are provided. In one aspect, a method includes: determining that a particular logical page in a logical block fails based on error bits in a particular physical page that is in a first physical block mapped with the logical block and corresponds to the particular logical page, logical pages in the logical block being mapped to physical pages in the first physical block with an initial mapping order, and executing a refresh operation on the first physical block with a rearranged mapping order for the logical block, the rearranged mapping order being different from the initial mapping order. For the refresh operation, the logical pages in the logical block are mapped to physical pages in a second physical block with the rearranged mapping order.
    Type: Application
    Filed: July 10, 2018
    Publication date: October 24, 2019
    Applicants: Macronix International Co., Ltd., MegaChips Corporation
    Inventors: Yuchih Yeh, Naping Kuo, Yuko Tamagawa