Abstract: A data transmission system comprising a plurality of connecting units, data lines interconnecting the connecting units in a sequence to form a data bus, and a plurality of data terminals. Each terminal is directly connected to a respective one of the connecting units to transmit data between the terminal and that connecting unit, and each connecting unit is switchable between normal and bypass states. In the normal state, each connecting unit transmits data from the immediately preceding connecting unit both to the next following connecting unit and to the terminal directly connected to the connecting unit, transmits data from the immediately preceding connecting unit to the next following connecting unit, and transmits data from the directly connected terminal to the next following connecting unit. In the bypass state, the connecting unit transmits data from the immediately preceding connecting unit to the next following connecting unit.

Abstract: The present invention generates a data clock for data processing circuitry by developing an optimum locally generated clock signal which is selected with each received data message. This is achieved by utilizing a local crystal clock which serves as an input to a multiple active parallel tap delay line. A register has the various delay signals input to it and a window generator strobes the inputs to the register so as to process the strobed levels of the various delayed clock signals. This is done to detect a level transition in any of the clock phases. Gating circuitry then chooses an optimum clock phase which has undergone a transition in a desired direction during the time window when the various clock phases were strobed. As a result of the present invention, utilized bandwidth may be increased and data distortion is minimized so that the number of stations connected to a data bus provided with the data clock of the invention may be increased substantially.

Abstract: A bus interface unit for interfacing a serial bit data bus to a parallel bit data handling system includes a receiver for acquiring serial data from the bus. A clock generates a clock signal at a frequency corresponding to frequency of bits in the serial data. A clock processor receives the serial data and the clock signal to generate a clock processor signal for processing the serial data. A serial to parallel converter responsive to the serial data and the clock processor signal converts the serial data to parallel bit data. An output driver provides the parallel bit data to the parallel bit data handling system. A frame check sequence tester responsive to the serial data and the clock signal provides a validity output signal when the frame check sequence is recognized by the tester. The tester includes a plurality of devices operating in parallel to increase speed. A serial to parallel converter converts data received from the parallel bit data handling device to serial form data.