Abstract: An overridable data protection mechanism for unlocking/locking a PLD includes a data protect override key register, an input key register, and a comparator. After the user inputs an access code to the input key register, the software program sends an enabling signal to the comparator which in turn compares the bits stored in the data protect override key register and the bits in the input key register. If the bits in the two registers are identical, then the comparator outputs a disable data protect signal, thereby allowing the user to modify the configuration data in that PLD. After an incremented version control number and the new configuration data are downloaded to the PLD, the program sends a disabling signal to the comparator, thereby preventing further modification to the configuration data on that PLD.

Abstract: An in-system programming/erasing/verifying structure for non-volatile programmable logic devices includes a data input pin, a data output pin, an instruction register, a plurality of data registers including an ISP register, wherein said instruction register and said plurality of data registers are coupled in parallel between said data input pin and said data output pin, and a controller for synchronizing said instruction register and said plurality of data registers. The ISP register includes: an address field, a data field, and a status field. An ISP instruction need only be entered once to program/erase the entire device. Specifically, the address/data packets can be shifted back to back into the ISP register without inserting multiple instructions between each packet at the data input pin, thereby dramatically decreasing the time required to program/erase the entire device in comparison to known ISP methods. Furthermore, the invention provides an efficient method for providing the status (i.e.

Abstract: An overridable data protection mechanism for unlocking/locking a PLD includes a data protect override key register, an input key register, and a comparator. After the user inputs an access code to the input key register, the software program sends an enabling signal to the comparator which in turn compares the bits stored in the data protect override key register and the bits in the input key register. If the bits in the two registers are identical, then the comparator outputs a disable data protect signal, thereby allowing the user to modify the configuration data in that PLD. After an incremented version control number and the new configuration data are downloaded to the PLD, the program sends a disabling signal to the comparator, thereby preventing further modification to the configuration data on that PLD.

Abstract: A programmable logic device (PLD) including configurable circuitry for altering the speed-versus-power characteristics of the PLD after production, and for allowing the PLD to selectively operate on either a 3.3-volt or a 5-volt power supply. The configurable circuitry includes an input buffer, an output buffer and a reference generator. The input buffer includes a dedicated P-channel transistor connected in series with a dedicated N-channel transistor, and a plurality of trip-point adjustment transistors which are selectively connected in parallel with the dedicated transistors to adjust the trip-point of the input buffer by altering the N-to-P ratio. The output buffer includes two configurable buffers whose trip-points are also adjustable. A configurable reference generator is also provided for generating a high precision reference voltage which is supplied to the sense amplifiers located in the function blocks and interconnect matrix of the PLD.

Abstract: A complex programmable logic device (PLD) that includes a number of programmable function blocks and an instruction bus for receiving programming instructions. The programming instructions are used to program the function blocks to enable the PLD to perform one or more desired logic functions. The PLD also includes an instruction-blocking circuit that is connected to each of the functional blocks. When directed by a user, the instruction blocking circuit selectively blocks programming instructions on the instruction bus from one or more of the function blocks while allowing the other function blocks to receive the programming instructions. Thus, one or more function blocks in the PLD are reprogrammed without interrupting the operation of the remaining function blocks.

Abstract: An in-system programing/erasing/verifying structure for non-volatile programable logic devices includes a data input pin, a data output pin, an instruction register, a plurality of data registers including an ISP register, wherein said instruction register and said plurality of data registers are coupled in parallel between said data input pin and said data output pin, and a controller for synchronizing said instruction register and said plurality of data registers. The ISP register includes: an address field, a data field, and a status field. An ISP instruction need only be entered once to program/erase the entire device. Specifically, the address/data packets can be shifted back to back into the ISP register without inserting multiple instructions between each packet at the data input pin, thereby dramatically decreasing the time required to program/erase the entire device in comparison to known ISP methods. Furthermore, the invention provides an efficient method for providing the status (i.e.

Abstract: A programmable logic device (PLD) includes test circuitry compatible with the JTAG standard (IEEE Standard 1149.1). The PLD also includes a programmable JTAG-disable bit that can be selectively programmed to disable the JTAG circuitry, leaving the PLD to operate as a conventional, non-JTAG-compatible PLD. The PLD also includes means for testing the JTAG test circuitry to determine whether the JTAG circuitry is defective, and means for programming the JTAG-disable bit to disable the JTAG circuitry if the testing means determines that the JTAG circuitry is defective.

Abstract: An integrated programmable logic device (PLD) includes flash EPROM storage transistors. The PLD includes a multiplexor that selectively provides program, erase, or verify voltages to the storage transistors. The program, erase, and verify voltages may be supplied using external power supplies or may be generated internally by on-chip charge-pump generators. A configurable memory on the PLD is used to adjust the output voltages from each of the on-chip charge-pump generators.

Abstract: A reconfigurable sense amplifier in accordance with the present invention operates in either a high switching speed mode, where power consumption is a less critical consideration, or in a low power consumption mode, where switching speed is a less critical consideration. In a high speed mode, the present invention provides an additional pull-up to an amplified bitline which in combination with an existing weak pull-up still permits the signal on the amplified bitline to be affected by a change in voltage on the bitline. In a low power mode, the present invention provides a temporary pull-up on the amplified bitline if a signal on a wordline is transitioning from high to low (i.e. indicating that a low-to-high signal transition may occur on the bitline). In this manner, the present invention anticipates that when such a transition occurs, the voltage on the amplified bitline may also increase.

Abstract: In an EPLD, a feedback switching circuit is provided on a feedback line connected between a macrocell output line and a interconnect matrix wordline, the switching circuit including a memory element and a switch for passing a macrocell output signal from the output line to the interconnect matrix wordline when the memory element is in a first state, and for blocking the macrocell output signal when the memory element is in a second state. This prevents coupling noise in the interconnect matrix because unnecessary feedback signals are prevented from entering the interconnect matrix. In another embodiment, a method is provided in which unused macrocells produce counteractive switching signals in the interconnect matrix to reduce the coupling effect caused by a multiple concurrent switching event. In another embodiment, a sense amplifier is provided in which an EPROM shields coupling between wordlines and bitlines in an interconnect matrix.

Abstract: A memory device, with increased storage speed and enhanced memory utilization, can be implemented by using multiplex clocking and efficient device design and enhanced flip-flop utilization. Transit time through the circuit, and hence circuit speed, can be controlled through multiplexed clock signals, and is increased by using fewer transistors in the signal path and allowing data to be transmitted directly to the flip-flop output by bypassing the flip-flop's master latch input.

Abstract: A programmable logic device having macrocells enables gate cascades between macrocells to occur with a faster signal transit time, while preserving the flip flop function of the cascaded macrocells by reallocating a redirectable flip flop reset product term to the flip flop input. All gate product terms are retained during cascading. The macrocell logic is optimized for fast signal transit with selectable flip flop clocking. Multiplex clocking and programming are done with fewer transistors in the signal path, further reducing signal transit time.

Abstract: A wordline driver for a wordline in an integrated programmable logic device (PLD) having flash memory cells. The wordline driver includes an input terminal that accepts a binary wordline input signal, a pass gate coupled to the input terminal and to a mode-control terminal, and an inverter that receives an input from the pass gate or the mode-control terminal, depending on the operating mode of the PLD. The output signal from the inverter is coupled to a multiplexer that selects between that output and a signal from a voltage supply, the signal selected depending on the operating mode of the PLD. The multiplexer outputs the selected signal to the wordline of the PLD.

Abstract: A reconfigurable sense amplifier in accordance with the present invention operates in either a high switching speed mode, where power consumption is a less critical consideration, or in a low power consumption mode, where switching speed is a less critical consideration. In a high speed mode, the present invention provides an additional pull-up to an amplified bitline which in combination with an existing weak pull-up still permits the signal on the amplified bitline to be affected by a change in voltage on the bitline. In a low power mode, the present invention provides a temporary pull-up on the amplified bitline if a signal on a wordline is transitioning from high to low (i.e. indicating that a low-to-high signal transition may occur on the bitline). In this manner, the present invention anticipates that when such a transition occurs, the voltage on the amplified bitline may also increase.

Abstract: An AND array for an erasable programmable logic device (EPLD) includes word-line transition detectors for indicating high-to-low word-line transitions. Such transitions are a condition precedent for low to-high bit line transitions. Transition indications are buffered by a fast transition-detection sense amplifier, the output of which is provided to each of plural "mode-switchable" sense amplifiers that read out the bit lines for the AND array. Each mode-switchable sense amplifier logically combines the transition indication with its own output to select its operating mode. A fast (strong source-current) mode is entered only when,the transition indication is active and the present output of the sense amplifier is low. Otherwise, which is most of the time, the mode switchable sense amplifier remains in a low-power (weak source-current) mode. This arrangement provides higher speed operation with relatively low time-averaged power consumption.

Abstract: A sense amplifier of the present invention provides power savings of between 30% to 70% for typical usage of a programmable logic device. In one embodiment, this sense amplifier includes circuitry for detecting and propagating the logic state on a bit line, an amplifier for amplifying the propagated logic state, and configuration logic for receiving a first configuration bit and a second configuration bit. If the first configuration bit and the second configuration bit have different logic states (indicating a non-toggling state), then the sense amplifier mimics the bit line at either a first logic state or a second logic state. Specifically, if the first configuration bit has the first logic state and the second configuration bit has the second logic state, then the sense amplifier mimics the bit line at the first logic state.

Abstract: A power-on reset circuit is provided which holds an integrated circuit device in a reset mode until at least two conditions are satisfied: supply voltage Vcc must be above a specified value and sense amplifiers in the device must be able to operate properly. Delay circuits and Schmitt trigger circuits also improve the stability of the signal which releases the device from its reset mode.

Abstract: A programmable logic device having macrocells enables gate cascades between macrocells to occur with a faster signal transit time, while preserving the flip flop function of the cascaded macrocells by reallocating a redirectable flip flop reset product term to the flip flop input. All gate product terms are retained during cascading. The macrocell logic is optimized for fast signal transit with selectable flip flop clocking. Multiplex clocking and programming are done with fewer transistors in the signal path, further reducing signal transit time.