Abstract: A method for transmitting data between a microprocessor and an external memory module through external package pins of the microprocessor, which includes the steps of: a) deciding N-bit full sized data to be transferred by using M, wherein N and M are positive integers and N is greater than M; b) sequentially transferring N/M number of M-bit divided data; c) temporarily storing N/M number of M-bit divided data; and d) combining the N/M number of M-bit divided data into the N-bit full sized data.

Abstract: A combined cache with main memory and a control method thereof, which can be configured with various structures of cache by only adding a minimized control circuit in order to be used as main memory. The N-way cache memory system includes N cache memory blocks receiving a tag field and an offset field of an address bus, a logic OR element for performing a logic OR operation with way hit signals from each cache memory block and for generating a cache hit signal when a way hit signal is produced in one of the cache memory blocks, and a first selection element for outputting data to a data bus, which results from the cache memory blocks in response to the way hit signal.