Patents by Inventor Narasimha Adiga

Narasimha Adiga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Feedback from higher-level verification to improve unit verification effectiveness
    Patent number: 11200125
    Abstract: Embodiments of the invention are directed to a computer-implemented method of unit environment verification. The method includes monitoring, by a processor, a data stream between a first driver and a device under test (DUT) in a unit verification environment. The processor retrieves a transaction value from a database, wherein the transaction value was generated in a higher-level verification environment than the unit verification environment. The processor transmits the retrieved transaction value to the DUT. The processor compares a response from the DUT to the transmitted transaction value to an expected value. In response to the comparison indicating an error, the processor initiates a repair of the error at the unit verification environment.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: December 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Narasimha Adiga, Madhusudan Kadiyala
  • FEEDBACK FROM HIGHER-LEVEL VERIFICATION TO IMPROVE UNIT VERIFICATION EFFECTIVENESS
    Publication number: 20200341875
    Abstract: Embodiments of the invention are directed to a computer-implemented method of unit environment verification. The method includes monitoring, by a processor, a data stream between a first driver and a device under test (DUT) in a unit verification environment. The processor retrieves a transaction value from a database, wherein the transaction value was generated in a higher-level verification environment than the unit verification environment. The processor transmits the retrieved transaction value to the DUT. The processor compares a response from the DUT to the transmitted transaction value to an expected value. In response to the comparison indicating an error, the processor initiates a repair of the error at the unit verification environment.
    Type: Application
    Filed: April 25, 2019
    Publication date: October 29, 2020
    Inventors: Narasimha Adiga, Madhusudan Kadiyala