Abstract: An apparatus to power up an integrated device from a low power state wherein the clock circuit for generating the internal clocks has been disabled is provided. A small set of programmable registers is reserved inside the CPU interface unit (CIF) of an integrated device (e.g., a display/graphics controller) which can be accessed by the CPU even during a low power state mode (e.g., software controlled sleep mode D3 in the preferred embodiment). The programmable registers store programmed bits that are used in indicating to the Power Management Unit (PMU) the desired power state and whether the clock circuits are to be enabled or disabled. The programmable registers also store multiplication and division factors to be used by the clock circuits in determining their clock rate. Using this information, the integrated device can go through a predetermined power sequence to transition from the low power state to the normal state which includes powering up the clock circuits (e.g., PLLs and oscillator).

Abstract: An apparatus that allows for high capacity and fast access command queuing without requiring excess host processor overhead clock gating apparatus that is cost efficient and allows power conservation is provided. A command and its associated data to be processed by a graphics engine are formatted as data structures and first stored in system memory. A number of these data structures can be queued in system memory at any given time. Each data structure includes a header that provides information related to the data words in the data structure such as the number of the data words involved, their destination address, and others. Using the header information provided, the command and its associated data are sequentially provided to the graphics engine for processing.

Abstract: A clock doubler circuit with duty cycle control includes an exclusive-OR, a toggle flip-flop, a plurality of control bit flip-flops, a primary delay element, a plurality of secondary delay elements, and a multiplexer. The toggle flip-flop has a clock input connected to an output of the exclusive-OR, and an inverted data output connected back to a data input of the toggle flip-flop and connected forward to an input of the primary delay element. An output of the primary delay element is connected to an input of the multiplexer and to individual inputs of the plurality of secondary delay elements which in turn, have outputs connected to other inputs of the multiplexer. A plurality of control bits generated, for example, by a computer program running on a host processor, are respectively provided to data inputs of the plurality of control bit flip-flops which in turn, have data outputs connected to select inputs of the multiplexer.

Abstract: A clock switching circuit responsive to at least one clock select signal switches to a selected one of a plurality of clock signals while minimizing transients generated during the switching. The circuit includes at least one flip-flop receiving a corresponding one of the at least one clock select signal; a plurality of flip-flops individually receiving an output of a corresponding one of the at least one flip-flop, and an inverted version of a corresponding one of the clock signals; a plurality of AND gates individually receiving the output of a corresponding one of the at least one flip-flop, the output of a corresponding one of the plurality of flip-flops, and a corresponding one of the plurality of clock signals; and an OR gate receiving the outputs of the AND gates so that the selected one of the plurality of clock signals is provided at an output of the OR gate, and fed back to an inverted clock input of the at least one flip-flop.