Patents by Inventor Narasimha R. Mavilla

Narasimha R. Mavilla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10164027
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: December 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mohit Bajaj, Suresh Gundapaneni, Aniruddha Konar, Narasimha R. Mavilla, Kota V. R. M. Murali, Edward J. Nowak
  • Patent number: 10163716
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: December 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mohit Bajaj, Suresh Gundapaneni, Aniruddha Konar, Narasimha R. Mavilla, Kota V. R. M. Murali, Edward J. Nowak
  • Publication number: 20180130655
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.
    Type: Application
    Filed: October 25, 2017
    Publication date: May 10, 2018
    Inventors: Mohit BAJAJ, Suresh GUNDAPANENI, Aniruddha KONAR, Narasimha R. Mavilla, Kota V.R.M. MURALI, Edward J. NOWAK
  • Patent number: 9911598
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: March 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mohit Bajaj, Suresh Gundapaneni, Aniruddha Konar, Narasimha R. Mavilla, Kota V. R. M. Murali, Edward J. Nowak
  • Publication number: 20180053828
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.
    Type: Application
    Filed: October 26, 2017
    Publication date: February 22, 2018
    Inventors: Mohit BAJAJ, Suresh GUNDAPANENI, Aniruddha KONAR, Narasimha R. Mavilla, Kota V.R.M. MURALI, Edward J. NOWAK
  • Patent number: 9876084
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: January 23, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mohit Bajaj, Suresh Gundapaneni, Aniruddha Konar, Narasimha R. Mavilla, Kota V. R. M. Murali, Edward J. Nowak
  • Publication number: 20170194467
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.
    Type: Application
    Filed: January 12, 2017
    Publication date: July 6, 2017
    Inventors: Mohit BAJAJ, Suresh GUNDAPANENI, Aniruddha KONAR, Narasimha R. Mavilla, Kota V.R.M. MURALI, Edward J. NOWAK
  • Patent number: 9613867
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: April 4, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mohit Bajaj, Suresh Gundapaneni, Aniruddha Konar, Narasimha R. Mavilla, Kota V. R. M. Murali, Edward J. Nowak
  • Publication number: 20170062594
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.
    Type: Application
    Filed: March 29, 2016
    Publication date: March 2, 2017
    Inventors: Mohit BAJAJ, Suresh GUNDAPANENI, Aniruddha KONAR, Narasimha R. Mavilla, Kota V.R.M. MURALI, Edward J. NOWAK
  • Publication number: 20170062234
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.
    Type: Application
    Filed: March 29, 2016
    Publication date: March 2, 2017
    Inventors: Mohit BAJAJ, Suresh GUNDAPANENI, Aniruddha KONAR, Narasimha R. Mavilla, Kota V.R.M. MURALI, Edward J. NOWAK
  • Patent number: 9379253
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: June 28, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mohit Bajaj, Suresh Gundapaneni, Aniruddha Konar, Narasimha R. Mavilla, Kota V. R. M. Murali, Edward J. Nowak