Abstract: An integrated circuit, such as a memory, having an internal data bus for communicating the output of a sense amplifier, is disclosed. The sense amplifiers are of the differential type, having first and second sense nodes at which the amplified differential signal appears. When unselected, or during precharge, each sense amplifier is precharged so that its sense nodes are at a power supply voltage, for example V.sub.cc. Each sense amplifier is connected to a data driver of the push-pull type, in such a manner that both the pull-up and pull-down transistors are off in the precharged or unselected state. This ability to tristate the data driver from the precharged state of the sense amplifier allows for the high impedance state to be entered without requiring an additional signal to be communicated thereto. Such operations as precharging the data bus conductors are thus facilitated, providing improved access time performance.

Abstract: A dynamic comparator circuit for a cache memory within a computer system is disclosed. In accordance with an illustrative embodiment of the present disclosure, the dynamic comparator circuit includes a first transistor, a first set of two transistors and a second set of two transistors. The first transistor is connected between an output and ground, having its gate connecting to a precharge signal. The first set of two transistors is connected in series between a power supply and the output. The gates of the first set of two transistors are separately connected to a first bit signal and a second bit signal. The second set of two transistors is also connected in series between the power supply and the output. The gates of the second set of two transistors are separately connected to a complement of the first bit signal and a complement of the second bit signal such that a transition occurs in an output signal when the first bit signal matches the second bit signal.

Abstract: An on-chip power supply regulation system for a VLSI circuit such as a dynamic RAM is disclosed. The system includes a high power supply voltage detection circuit and a power supply clamp circuit, where a clamped voltage generated by the clamp circuit biases the functional circuitry when the high power supply voltage detection circuit detects an overvoltage condition. The bias voltage applied to the functional circuitry in the normal operating condition can be a regulated voltage generated from the power supply voltage. Further included in the disclosed circuit is a burn-in voltage generation circuit and a burn-in voltage detection circuit, which can apply an accelerated voltage which depends upon the applied power supply voltage, when the power supply voltage is higher than during normal operation but lower than in the overvoltage condition enabling the clamp operation.

Abstract: An integrated circuit having a memory with a parallel test data comparator is disclosed. The parallel test data comparator includes a NOR-like function which has parallel transistors having their gates connected to an input from each of the internal data lines, and a NAND-like function which also has parallel transistors having their gates connected to an input from each of the internal data lines. The output nodes of each function are biased by single transistors, each controlled by a test enable signal, and each of which can be overpowered by any one of the parallel transistors. In the event that all of the internal data lines are at the same logic level, the outputs of the NOR and NAND will be at the same logic level; conversely, if any one (or more) of the internal data lines is different from the rest, the outputs of the NOR and NAND will be at different logic levels. An exclusive-OR-like function is used to generate a pass or fail signal responsive to the output nodes of the NOR and NAND.

Abstract: An integrated circuit memory is disclosed which has its primary memory array arranged into blocks and which has redundant columns, each of which can replace a column in any one of the blocks. The redundant columns are selected by way of a redundant column decoder, associated with each column. A plurality of redundant sense amplifiers are each associated with selected redundant columns. Each of the redundant column decoders includes a set of fuses for storing the column address responsive to which its associated redundant column is to be selected. The coupling of each redundant sense amplifier is controlled by a redundant multiplexer associated with each of the input/output terminals. Each redundant multiplexer receives the redundant column select signals from each redundant column decoder corresponding thereto, and includes fuses which indicate if its input/output terminal is to be placed in communication with its associated sense amplifier upon selection of a redundant column.

Abstract: A circuit for providing a bias to the substrate of a dynamic memory device having a memory array and peripheral circuitry formed in a semiconductor substrate is disclosed. The circuit includes a low power pump and oscillator to provide a substrate bias in a memory standby mode. A high power pump and oscillator is included to provide a substrate bias when the memory is active. A booster oscillator and pump to provide a substrate bias when the memory is active and when the substrate voltage level is greater than a preset level is also provided. A method for contolling the voltage level of the substrate upon which a dynamic memory device is formed is also disclosed.

Abstract: A substrate bias detection circuit is disclosed. The circuit includes first and second transistors, where the first transistor has its source coupled to the substrate and where the second transistor has its source coupled to a common potential (i.e., ground). The gate and drain of the first transistor are connected together, and to the gate of the second transistor. Load devices are connected between the drains of the first and second transistors and a bias potential from a power supply node. The threshold voltages of the first and second transistors may be different, with the difference determining the voltage that the substrate must reach, relative to the common potential, to cause the circuit to respond. Upon the substrate reaching a voltage sufficient to turn the second transistor on, the drain of the second transistor will be pulled toward the common potential, indicating loss of substrate bias.

Abstract: An on-chip power supply regulation system for a VLSI circuit such as a dynamic RAM is disclosed. The system includes a high power supply voltage detection circuit and a power supply clamp circuit, where a clamped voltage generated by the clamp circuit biases the functional circuitry when the high power supply voltage detection circuit detects an overvoltage conditions. The bias voltage applied to the functional circuitry in the normal operating condition can be a regulated voltage generated from the power supply voltage. Further included in the disclosed circuit is a burn-in voltage generation circuit and a burn-in voltage detection circuit, which can apply an accelerated voltage which depends upon the applied power supply voltage, when the power supply voltage is higher than during normal operation but lower than in the overvoltage condition enabling the clamp operation.