Abstract: A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) for generating at least one bias voltage and at least one slave delay locked loop (“SDLL”). The at least one SDLL is coupled to the MDLL, where the at least one SDLL comprises an analog to digital converter for converting the at least one bias voltage to at least one digital signal, an adder/subtractor block for adjusting the at least one digital signal based on at least one control signal, a digital to analog converter for converting the at least one adjusted digital signal to at least one analog signal, a voltage to current converter for converting the at least one analog signal to at least one bias current, delay elements for generating phase delayed signals based on the at least one bias current, and a phase detector and control logic for determining any phase difference between the phase delayed signals and for generating the at least one control signal to align the phase delayed signals.

Abstract: A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) and at least one slave delay locked loop (“SDLL”). The MDLL generates one or more biases. Each of the at least one SDLL has a slave calibration unit and slave delay elements. The slave calibration unit calibrates the slave delay elements using a slave calibration loop and the generated one or more bias. Thus, each of the SDLL is calibrated to account for any electrical noise, pressure, voltage, and temperature variations that the respective SDLL experiences.

Abstract: A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) for generating at least one bias voltage and at least one slave delay locked loop (“SDLL”). The at least one SDLL is coupled to the MDLL, where the at least one SDLL comprises an analog to digital converter for converting the at least one bias voltage to at least one digital signal, an adder/subtractor block for adjusting the at least one digital signal based on at least one control signal, a digital to analog converter for converting the at least one adjusted digital signal to at least one analog signal, a voltage to current converter for converting the at least one analog signal to at least one bias current, delay elements for generating phase delayed signals based on the at least one bias current, and a phase detector and control logic for determining any phase difference between the phase delayed signals and for generating the at least one control signal to align the phase delayed signals.

Abstract: A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) and at least one slave delay locked loop (“SDLL”). The MDLL generates one or more biases. Each of the at least one SDLL has a slave calibration unit and slave delay elements. The slave calibration unit calibrates the slave delay elements using a slave calibration loop and the generated one or more bias. Thus, each of the SDLL is calibrated to account for any electrical noise, pressure, voltage, and temperature variations that the respective SDLL experiences.

Abstract: A receiver architecture for memory reads is described herein. In one embodiment, a memory interface comprises a plurality of transmitters, wherein each of the plurality of transmitters is configured to transmit data to a memory device over a respective one of a plurality of I/O channels. The memory interface also comprises a plurality of receivers, wherein each of the plurality of receivers is coupled to a respective one of the plurality of transmitters, and is configured to receive data from the memory device over the respective one of the plurality of I/O channels. The plurality of receivers are grouped together into a receiver subsystem that is located away from the plurality of transmitters.

Abstract: Techniques for reducing cross-supply current are described herein. In one embodiment, a power circuit comprises a bypass switch coupled between a first power supply and an internal power supply, and a voltage regulator coupled between a second power supply and the internal power supply. The power circuit also comprises a shut-off circuit configured to detect the first power supply powering up before the second power supply during a power-up sequence, to shut off the bypass switch upon detecting the first power supply powering up before the second power supply, to detect the second power supply powering up during the power-up sequence, and to release control of the bypass switch to a controller upon detecting the second power supply powering up.

Abstract: A delay architecture for reducing downtime during frequency switching is described herein. In one embodiment, an adjustable delay circuit comprises a phase-locked loop (PLL) or a delay-locked loop (DLL) configured to generate a bias voltage, and a plurality of delay elements coupled in series, wherein each of the delay elements is biased by the bias voltage. The adjustable delay circuit also comprises a multiplexer coupled to outputs of two or more of the delay elements, wherein each of the outputs corresponds to a different delay of an input signal, and wherein the multiplexer is configured to select one of the outputs based on a data frequency of a memory interface.

Abstract: A receiver architecture for memory reads is described herein. In one embodiment, a memory interface comprises a plurality of transmitters, wherein each of the plurality of transmitters is configured to transmit data to a memory device over a respective one of a plurality of I/O channels. The memory interface also comprises a plurality of receivers, wherein each of the plurality of receivers is coupled to a respective one of the plurality of transmitters, and is configured to receive data from the memory device over the respective one of the plurality of I/O channels. The plurality of receivers are grouped together into a receiver subsystem that is located away from the plurality of transmitters.

Abstract: A semiconductor device having a phase-locked loop (“PLL”) (100) drives a VCO (114) of the PLL circuit with a first control voltage (VCTRL) produced by a loop filter (112) when a first clock signal (clk_ref) is present. The VCO produces an output frequency while the PLL circuit is operating off the first clock signal. When the first clock signal is lost (ref_lost), a control voltage maintenance circuit (120) produces a second control voltage maintaining the VCO output frequency. In one device, the control voltage maintenance circuit includes a phase-frequency detector (104) that can operate off of either the clock reference signal or a master clock signal. In an alternative device, the control voltage maintenance circuit includes a voltage generator (334, 362) that produces a generated voltage that drives the loop filter when lock is lost.

Abstract: A method and apparatus involving a circuit is disclosed. The circuit has separate first and second portions, where the first portion includes a first memory device such as a flip-flop, and the second portion includes a second memory device such as a latch. The first portion is selectively operated in first and second operational modes, the first portion consuming less power in the second operational mode than in the first operational mode. During the first operational mode a logical value is maintained in the flip-flop and can vary dynamically. During the second operational mode, the state that the logical value had at a point in time just before the first portion entered the second operational mode is maintained in the latch. Then, after the first portion switches from the second operational mode back to the first operational mode, the state of the logical value in the latch is restored to the flip-flop.

Abstract: A voltage regulator for supplying power to volatile memory cells during a suspend mode of an integrated circuit is described. The integrated circuit in an awake mode generates a regulated voltage at an output node using a first supply voltage and in the suspend mode generates the regulated voltage at the output node using a second supply voltage, at less voltage than the first supply voltage. The second supply voltage is electrically decoupled from the output node for transitioning from the suspend mode to the awake mode, and the first supply voltage is electrically decoupled from the output node for transitioning from the awake mode to the suspend mode.

Abstract: A method and apparatus is provided that facilitates low-power consumption during a suspend mode of operation of an integrated circuit (IC), while substantially eliminating current paths within the IC that may be created should any of the power supplies be deactivated during the suspend mode. Deactivation of one or more power supplies during a normal mode of operation is also facilitated, whereby current paths created by the deactivated power supplies are also eliminated. Voltage bias circuitry is added to certain voltage regulators within the IC, so as to maintain those voltage regulators inactive due to a drop in voltage magnitude that is sensed when one or more power supplies are disabled. In addition, a well bias circuit is employed to maintain the substrate bias potential of certain devices within the voltage regulators and associated amplifiers to a fixed potential depending upon the operational mode of the IC.

Abstract: A voltage regulator and method of voltage regulation for a power-on reset condition are described. Voltage regulation control signals responsive to the power-on reset condition are obtained. The control signals are generated with a first voltage to be associated with a second voltage to provide a first power-on-reset signal and a second power-on-reset signal which are opposite in state to one another. A portion of driver logic is tri-stated responsive to the control signals, and the second power-on-reset signal to at least impede supply to supply current leakage. Voltage is pulled up on a first output port and a second output port of the driver logic responsive to the first power-on-reset signal. A portion of a semiconductor substrate is electrically coupled to a higher one of a first voltage and a second voltage responsive to the pulling up to at least further impede the supply to supply current leakage.

Abstract: A bandgap reference voltage circuit includes a bandgap circuit, a start-up circuit, and a recovery circuit. Upon device power-on, the start-up circuit provides a start-up current to initialize the bandgap circuit to a valid state, during which the bandgap circuit generates a substantially constant bandgap reference voltage. Once the bandgap circuit is in the valid state, the start-up circuit turns itself off. If the bandgap reference voltage falls to a level that causes the bandgap circuit to enter an invalid state, the recovery circuit turns on and provides a recovery current to the bandgap circuit that returns the bandgap circuit to the valid state, after which the recovery circuit turns itself off.

Abstract: A voltage supply circuit for generating a composite bandgap reference voltage includes a single bandgap reference voltage circuit and a select circuit. The bandgap reference circuit has a first output to generate a first bandgap voltage having a first temperature coefficient and has a second output to generate a second bandgap voltage having a second temperature coefficient that is different from the first temperature coefficient. The select circuit has a first input to receive the first bandgap voltage, a second input to receive the second bandgap voltage, and an output to selectively provide either the first bandgap voltage or the second bandgap voltage as the composite bandgap reference voltage.

Abstract: An integrated circuit (IC) device includes a first voltage supply for powering first circuitry within the device, a second voltage supply for powering second circuitry within the device, a suspend circuit having an output to generate a power-down signal, and a voltage regulator circuit coupled to a power node. The voltage regulator circuit includes a first transistor coupled between the first voltage supply and the power node and having a gate responsive to a regulation signal, a second transistor coupled between the second voltage supply and the power node and having a gate responsive to the power-down signal, and a well bias circuit having an input coupled to receive the power-down signal, a first output coupled to a well region of the first transistor, and a second output coupled to a well region of the second transistor.

Abstract: A test structure provides defect information rapidly and accurately. The test structure includes a plurality of lines provided in a parallel orientation, a decoder coupled to the plurality of lines for selecting one of the plurality of lines, and a sense amplifier coupled to the selected line. To analyze an open, a line in the test structure is coupled to the sense amplifier. A high input signal is provided to the line. To determine the resistance of the open, a plurality of reference voltages are then provided to the sense amplifier. A mathematical model of the resistance of the line based on the reference voltage provided to the sense amplifier is generated. Using this mathematical model, the test structure can quickly detect and characterize defect levels down to a few parts-per-million at minimal expense.