Abstract: The present invention provides a system and method for optimizing BOM cost of platform SoC for Battery management system. The system (100) comprises a sensor (101), coupled with the device to receive input physical parameters Temperature, Voltage and current and a CPU with SIMD extensions without saturation logic in the instruction set and floating-point unit, wherein Battery management module is implemented (101). Using CPU with SIMD extensions instead of DSPNLIW core in platform SoC helps in lowering the BoM cost and the inventive steps helps in achieving bit-exact results overcoming the limitations of CPU ISA as against DSP ISA. The power consumed in either case (Battery management implementation on CPU, DSP ISA) is the same, thus giving value additions to platform SoC designers and makers.

Abstract: The present invention provides a system and method for extracting Tropological features from an image. The system (100) comprises CPU core with Single Instruction Multiple Data (SIMD) instruction set but the instructions lack saturation logic (101), wherein the software modules are implemented. Removing the logic hardware used to implement saturation in the SIMD instructions helps in lowering the BoM cost and the inventive steps helps in achieving bit-exact results without saturation logic. The power consumed using CPU without saturation logic in SIMD instruction is lesser than using Digital Signal Processing Instruction Set Architecture with saturation logic, thus giving value additions to platform SoC designers and makers for using low BoM cost solution.

Abstract: The present invention provides a system and method for optimizing BoM cost and power performance drones. The system (100) comprises dual CPU cores with Single Instruction Multiple Data (SIMD) instruction set but the instructions lack saturation logic (101), wherein control software modules is implemented. Video codec encoder modules (102) are implemented in the second CPU with SIMD instruction set lacking saturation logic. Removing the logic hardware used to implement saturation in the SIMD instructions helps in lowering the BoM cost and the inventive steps helps in achieving bit-exact results without saturation logic. The power consumed using CPU without saturation logic in SIMD instruction is lesser than using Digital Signal Processing Instruction Set Architecture with saturation logic, thus giving value additions to platform SoC designers and makers for using low BoM cost solution with better power performance.

Abstract: The present invention provides a system and method for detection and identification of feature sub-image in a given image. The system (100) comprises single CPY core with Single Instruction Multiple Data (SIMD) instruction set but the instructions lack saturation logic (101), wherein the software modules are implemented. Removing the logic hardware used to implement saturation in the SIMD instructions helps in lowering the BoM cost and the inventive steps helps in achieving bit-exact results without saturation logic. The power consumed using CPU without saturation logic in SIMD instruction is lesser than using Digital Signal Processing Instruction Set Architecture with saturation logic, thus giving value additions to platform SoC designers and makers for using low BoM cost solution.

Abstract: The present invention provides a system and method for optimizing BOM cost of Graphics Processing Unit GPU core. The system (100) comprises a GPU with typical compute unit and instruction set of a GPU but the video SIMD instructions lacking saturation logic (101), wherein Video codec encoder/decoder modules is implemented. In-loop Deblocking filter, post-processing filtering module (102) are implemented in the GPU. Removing the logic hardware used to implement saturation in the video SIMD instructions helps in lowering the BoM cost and the inventive steps helps in achieving bit-exact results without saturation logic. The power consumed without saturation logic is lesser than one in with saturation logic is used, thus giving value additions to platform SoC designers and makers for using lo BoM cost GPU with better power performance.

Abstract: The present invention provides a system and method for optimizing BOM cost of platform SoC for Battery management system. The system (100) comprises a sensor (101), coupled with the device to receive input physical parameters Temperature, Voltage and current and a CPU with SIMD extensions without saturation logic in the instruction set and floating-point unit, wherein Battery management module is implemented (101). Using CPU with SIMD extensions instead of DSPNLIW core in platform SoC helps in lowering the BoM cost and the inventive steps helps in achieving bit-exact results overcoming the limitations of CPU ISA as against DSP ISA. The power consumed in either case (Battery management implementation on CPU, DSP ISA) is the same, thus giving value additions to platform SoC designers and makers.

Abstract: The present invention provides a system and method for optimizing power consumption in Multimedia Signal Processing in mobile devices. The system comprises a Media (speech, audio, image, and video) codec encoder module, a Media codec decoder module (106) and pre-processing and postprocessing (filtering, deblocking filter, Analytics, person detect, keyword/keyframe spotting) modules modules. The pre-processing and post-processing modules are implemented on a DSPNLIW processor, while the Media encoder and decoder modules are implemented on a CPU with SIMD extensions. This pipeline (asynchronous RPC, non-blocking) implementation of modules in multi-core reduces current consumption in the SoC by up to 50 percent compared to an implementation of the modules in a multiple CPU/DSP/VLIW core with synchronous RPC (blocking). The significant reduction in current consumption of the modules enables reduction of power consumption in the Multimedia processing use case.

Abstract: The present invention provides a system and method for optimizing BoM cost of platform SoC in mobile devices. The system (100) comprises a CPU with SIMD extensions wherein video codec encoder/decoder module is implemented (101), and another CPU with SIMD extensions instead of DSP/VLIW core wherein post-processing filtering module (Deblocking filter) (102) module is implemented. Replacing DSP/VLIW core in platform SoC helps in lowering the BoM cost and the inventive steps helps in achieving bit-exact results overcoming the limitations of CPU ISA as against DSP ISA. The power consumed is either case (deblocking filter on CPU, DSP ISA) is the same, thus giving value additions to platform SoC designers and makers.

Abstract: The present invention provides a system and method for optimizing power consumption in voice communication in mobile devices. The system comprises pre-processing modules, a speech codec encoder module, a speech codec decoder module and post-processing modules. The pre-processing and post-processing modules are implemented on a DSP/VLIW processor, while the speech encoder and decoder modules are implemented on a CPU with SIMD extensions. This pipelined implementation of modules in multi-core reduces current consumption in the SoC by up to 50 percent compared to an implementation of the modules in a single DSP/VLIW core. The significant reduction in current consumption of the modules enables reduction of power consumption in the talk time.

Abstract: The present invention provides a system and method for optimizing power consumption in video communication in mobile devices. The system comprises a video codec encoder module, a video codec decoder module and post-processing filtering module (Deblocking filter) modules. The post-processing modules are implemented on a DSP/VLIW processor, while the video encoder and decoder modules are implemented on a CPU with SIMD extensions. This pipelined implementation of modules in multi-core reduces current consumption in the SoC by up to 50 percent compared to an implementation of the modules in a single/multiple DSP/VLIW core. The significant reduction in current consumption of the modules enables reduction of power consumption in the video call time. Thus, the invention provides a simple method of optimizing power consumption by multi core implementation of the modules in a video call in mobile devices.

Abstract: The present invention provides a system and method for optimizing power consumption in Multimedia Signal Processing in mobile devices. The system comprises a Media (speech, audio, image, and video) codec encoder module, a Media codec decoder module (106) and pre-processing and postprocessing (filtering, deblocking filter, Analytics, person detect, keyword/keyframe spotting) modules modules. The pre-processing and post-processing modules are implemented on a DSPNLIW processor, while the Media encoder and decoder modules are implemented on a CPU with SIMD extensions. This pipeline (asynchronous RPC, non-blocking) implementation of modules in multi-core reduces current consumption in the SoC by up to 50 percent compared to an implementation of the modules in a multiple CPU/DSP/VLIW core with synchronous RPC (blocking). The significant reduction in current consumption of the modules enables reduction of power consumption in the Multimedia processing use case.

Abstract: The present invention provides a system and method for optimizing power consumption in video communication in mobile devices. The system comprises a video codec encoder module, a video codec decoder module and post-processing filtering module (Deblocking filter) modules. The post-processing modules are implemented on a DSP/VLIW processor, while the video encoder and decoder modules are implemented on a CPU with SIMD extensions. This pipelined implementation of modules in multi-core reduces current consumption in the SoC by up to 50 percent compared to an implementation of the modules in a single/multiple DSP/VLIW core. The significant reduction in current consumption of the modules enables reduction of power consumption in the video call time. Thus, the invention provides a simple method of optimizing power consumption by multi core implementation of the modules in a video call in mobile devices.

Abstract: The present invention provides a system and method for optimizing power consumption in voice communication in mobile devices. The system comprises pre-processing modules, a speech codec encoder module, a speech codec decoder module and post-processing modules. The pre-processing and post-processing modules are implemented on a DSP/VLIW processor, while the speech encoder and decoder modules are implemented on a CPU with SIMD extensions. This pipelined implementation of modules in multi-core reduces current consumption in the SoC by up to 50 percent compared to an implementation of the modules in a single DSP/VLIW core. The significant reduction in current consumption of the modules enables reduction of power consumption in the talk time.

Abstract: The present invention provides a system and method for optimizing power consumption in mobile devices. The system comprises a speech codec encoder module and a speech codec decoder module. The number of CPU/DSP/VLIW processor cycles taken to encode and decode the speech signals are significantly reduced to draw lower current by the mobile device. The significant reduction of processor cycles in the speech codec modules enables reduction of power consumption in the talk time. Thus, the invention provides a simple method of optimizing power consumption by reducing number of processor cycles to compress/decompress speech signal of the speech codec modules in mobile devices.