Patents by Inventor Narasimhulu Dharani Kotte
Narasimhulu Dharani Kotte has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240362111Abstract: In one embodiment, a solid state drive (SSD) comprises a plurality of non-volatile memory dies communicatively arranged in one or more communication channels, each of the plurality of non-volatile memory dies comprising a plurality of physical blocks, one or more channel controllers communicatively coupled to the one or more communication channels, respectively, and a memory controller communicatively coupled to the plurality of non-volatile memory dies via the one or more channel controllers, wherein the memory controller is configured to assign (i) the plurality of physical blocks of a first die of the plurality of non-volatile memory dies to only a first region and (ii) the plurality of physical blocks of a second die of the plurality of non-volatile memory dies to only a second region, perform only read operations on the first region in a first operation mode, and perform write operations or maintenance operations on the second region in a second operation mode concurrently with read operations on the firType: ApplicationFiled: July 8, 2024Publication date: October 31, 2024Applicant: Kioxia CorporationInventors: Steven Wells, Mark Carlson, Amit Jain, Narasimhulu Dharani Kotte, Senthil Thangaraj, Barada Mishra, Girish Desai
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Patent number: 12032438Abstract: In one embodiment, a solid state drive (SSD) comprises a plurality of non-volatile memory dies communicatively arranged in one or more communication channels, each of the plurality of non-volatile memory dies comprising a plurality of physical blocks, one or more channel controllers communicatively coupled to the one or more communication channels, respectively, and a memory controller communicatively coupled to the plurality of non-volatile memory dies via the one or more channel controllers, wherein the memory controller is configured to assign (i) the plurality of physical blocks of a first die of the plurality of non-volatile memory dies to only a first region and (ii) the plurality of physical blocks of a second die of the plurality of non-volatile memory dies to only a second region, perform only read operations on the first region in a first operation mode, and perform write operations or maintenance operations on the second region in a second operation mode concurrently with read operations on the firType: GrantFiled: March 21, 2022Date of Patent: July 9, 2024Assignee: KIOXIA CORPORATIONInventors: Steven Wells, Mark Carlson, Amit Jain, Narasimhulu Dharani Kotte, Senthil Thangaraj, Barada Mishra, Girish Desai
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Publication number: 20220214834Abstract: In one embodiment, a solid state drive (SSD) comprises a plurality of non-volatile memory dies communicatively arranged in one or more communication channels, each of the plurality of non-volatile memory dies comprising a plurality of physical blocks, one or more channel controllers communicatively coupled to the one or more communication channels, respectively, and a memory controller communicatively coupled to the plurality of non-volatile memory dies via the one or more channel controllers, wherein the memory controller is configured to assign (i) the plurality of physical blocks of a first die of the plurality of non-volatile memory dies to only a first region and (ii) the plurality of physical blocks of a second die of the plurality of non-volatile memory dies to only a second region, perform only read operations on the first region in a first operation mode, and perform write operations or maintenance operations on the second region in a second operation mode concurrently with read operations on the firType: ApplicationFiled: March 21, 2022Publication date: July 7, 2022Inventors: Steven Wells, Mark Carlson, Amit Jain, Narasimhulu Dharani Kotte, Senthil Thangaraj, Barada Mishra, Girish Desai
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Patent number: 11294594Abstract: In one embodiment, a solid state drive (SSD) comprises a plurality of non-volatile memory dies communicatively arranged in one or more communication channels, each of the plurality of non-volatile memory dies comprising a plurality of physical blocks, one or more channel controllers communicatively coupled to the one or more communication channels, respectively, and a memory controller communicatively coupled to the plurality of non-volatile memory dies via the one or more channel controllers, wherein the memory controller is configured to assign (i) the plurality of physical blocks of a first die of the plurality of non-volatile memory dies to only a first region and (ii) the plurality of physical blocks of a second die of the plurality of non-volatile memory dies to only a second region, perform only read operations on the first region in a first operation mode, and perform write operations or maintenance operations on the second region in a second operation mode concurrently with read operations on the firType: GrantFiled: November 1, 2017Date of Patent: April 5, 2022Assignee: Kioxia CorporationInventors: Steven Wells, Mark Carlson, Amit Jain, Narasimhulu Dharani Kotte, Senthil Thangaraj, Barada Mishra, Girish Desai
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Publication number: 20190042150Abstract: In one embodiment, a solid state drive (SSD) comprises a plurality of non-volatile memory dies communicatively arranged in one or more communication channels, each of the plurality of non-volatile memory dies comprising a plurality of physical blocks, one or more channel controllers communicatively coupled to the one or more communication channels, respectively, and a memory controller communicatively coupled to the plurality of non-volatile memory dies via the one or more channel controllers, wherein the memory controller is configured to assign (i) the plurality of physical blocks of a first die of the plurality of non-volatile memory dies to only a first region and (ii) the plurality of physical blocks of a second die of the plurality of non-volatile memory dies to only a second region, perform only read operations on the first region in a first operation mode, and perform write operations or maintenance operations on the second region in a second operation mode concurrently with read operations on the firType: ApplicationFiled: November 1, 2017Publication date: February 7, 2019Inventors: Steven Wells, Mark Carlson, Amit Jain, Narasimhulu Dharani Kotte, Senthil Thangaraj, Barada Mishra, Girish Desai
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Patent number: 10095626Abstract: A solid state drive (SSD) with pseudo-single-level cell (pSLC) caching and a method of caching data in an SSD is disclosed. In one embodiment, the SSD includes a plurality of multibit NAND media devices arranged in one or more channels communicatively coupled to a memory controller. A first portion of the plurality of multibit NAND media devices is configured to operate as a pSLC cache and a second portion of the plurality of multibit NAND media devices is configured to operate as a multibit NAND media storage area. In one embodiment, the pSLC cache comprises a first area for a pSLC write cache and a second area for a pSLC read cache.Type: GrantFiled: March 10, 2017Date of Patent: October 9, 2018Assignee: Toshiba Memory CorporationInventors: Narasimhulu Dharani Kotte, Senthil Thamgaraj, Robert Reed, Hitoshi Kondo
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Publication number: 20180260331Abstract: A solid state drive (SSD) with pseudo-single-level cell (pSLC) caching and a method of caching data in an SSD is disclosed. In one embodiment, the SSD includes a plurality of multibit NAND media devices arranged in one or more channels communicatively coupled to a memory controller. A first portion of the plurality of multibit NAND media devices is configured to operate as a pSLC cache and a second portion of the plurality of multibit NAND media devices is configured to operate as a multibit NAND media storage area. In one embodiment, the pSLC cache comprises a first area for a pSLC write cache and a second area for a pSLC read cache.Type: ApplicationFiled: March 10, 2017Publication date: September 13, 2018Inventors: Narasimhulu Dharani Kotte, Senthil Murugan Thangaraj, Robert Reed, Hitoshi Kondo
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Publication number: 20180260342Abstract: A mass storage device and a method for wirelessly transmitting a first information by a mass storage device is disclosed. In one embodiment, the mass storage device includes one or more memory devices and a mass storage device controller communicatively coupled to the one or more memory devices. The mass storage device controller includes one or more controller processors and a wireless sideband interface. The wireless sideband interface is configured to wirelessly transmit the first information retrieved by an interface processor of the wireless sideband interface from one of the controller processors or one of the memory devices. In one embodiment, the interface processor is an internet-of-things (IoT) processor.Type: ApplicationFiled: March 10, 2017Publication date: September 13, 2018Inventors: Senthil Murugan Thangaraj, Narasimhulu Dharani Kotte, Chayan Biswas, Robert Reed, Hitoshi Kondo
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Patent number: 10049047Abstract: A solid state drive (SSD) with pseudo-single-level cell (pSLC) caching and a method of caching data in an SSD is disclosed. In one embodiment, the SSD includes a plurality of multibit NAND media devices arranged in one or more channels communicatively coupled to a memory controller. The SSD further includes one or more volatile memory devices communicatively coupled to the memory controller, where at least one of the one or more volatile memory devices has a read cache area. A first portion of the plurality of multibit NAND media devices is configured to operate as a pSLC write cache and a second portion of the plurality of multibit NAND media devices is configured to operate as a multibit NAND media storage area.Type: GrantFiled: March 10, 2017Date of Patent: August 14, 2018Assignee: Toshiba Memory CorporationInventors: Narasimhulu Dharani Kotte, Senthil Thamgaraj, Robert Reed, Hitoshi Kondo