Patents by Inventor Narasimhulu Dharanikumar Kotte
Narasimhulu Dharanikumar Kotte has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11531622Abstract: Systems and methods are disclosed including a processing device operatively coupled to a first and a second memory device. The processing device can receive a set of data access requests, from a host system, in a first order and execute the set of data access requests in a second order. The processing device can further identify a late data access request of the set of data access requests and determine whether a data structure in a local memory associated with the processing device includes a previous outstanding data access request corresponding to an address associated with the late data access request. Responsive to determining that the data structure includes an indication of a previous outstanding data access request corresponding to the address associated with the late data access request, identifying a type of data dependency associated with the previous outstanding data access request and performing one or more operations associated with the type of data dependency.Type: GrantFiled: August 26, 2020Date of Patent: December 20, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Horia C. Simionescu, Chung Kuang Chin, Paul Stonelake, Narasimhulu Dharanikumar Kotte
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Patent number: 11494306Abstract: Systems and methods are disclosed including a first memory component, a second memory component having a lower access latency than the first memory component and acting as a cache for the first memory component, and a processing device operatively coupled to the first and second memory components. The processing device can perform operations including receiving a data access operation and, responsive to determining that a data structure includes an indication of an outstanding data transfer of data associated with a physical address of the data access operation, determining whether an operation to copy the data, associated with the physical address, from the first memory component to the second memory component is scheduled to be executed. The processing device can further perform operations including determining to delay a scheduling of an execution of the data access operation until the operation to copy the data is executed.Type: GrantFiled: August 26, 2020Date of Patent: November 8, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Horia C. Simionescu, Chung Kuang Chin, Paul Stonelake, Narasimhulu Dharanikumar Kotte
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Patent number: 11397683Abstract: Systems and methods are disclosed including a first memory device, a second memory device coupled to the first memory device, where the second memory device has a lower access latency than the first memory device and acts as a cache for the first memory device. A processing device operatively coupled to the first and second memory devices can track access statistics of segments of data stored at the second memory device, the segments having a first granularity, and determine to update, based on the access statistics, a segment of data stored at the second memory device from the first granularity to a second granularity. The processing device can further retrieve additional data associated with the segment of data from the first memory device and store the additional data at the second memory device to form a new segment having the second granularity.Type: GrantFiled: August 26, 2020Date of Patent: July 26, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Horia C. Simionescu, Paul Stonelake, Chung Kuang Chin, Narasimhulu Dharanikumar Kotte, Robert M. Walker, Cagdas Dirik
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Publication number: 20210089450Abstract: Systems and methods are disclosed including a processing device operatively coupled to a first and a second memory device. The processing device can receive a set of data access requests, from a host system, in a first order and execute the set of data access requests in a second order. The processing device can further identify a late data access request of the set of data access requests and determine whether a data structure in a local memory associated with the processing device includes a previous outstanding data access request corresponding to an address associated with the late data access request. Responsive to determining that the data structure includes an indication of a previous outstanding data access request corresponding to the address associated with the late data access request, identifying a type of data dependency associated with the previous outstanding data access request and performing one or more operations associated with the type of data dependency.Type: ApplicationFiled: August 26, 2020Publication date: March 25, 2021Inventors: Horia C. Simionescu, Chung Kuang Chin, Paul Stonelake, Narasimhulu Dharanikumar Kotte
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Publication number: 20210089449Abstract: Systems and methods are disclosed including a first memory component, a second memory component having a lower access latency than the first memory component and acting as a cache for the first memory component, and a processing device operatively coupled to the first and second memory components. The processing device can perform operations including receiving a data access operation and, responsive to determining that a data structure includes an indication of an outstanding data transfer of data associated with a physical address of the data access operation, determining whether an operation to copy the data, associated with the physical address, from the first memory component to the second memory component is scheduled to be executed. The processing device can further perform operations including determining to delay a scheduling of an execution of the data access operation until the operation to copy the data is executed.Type: ApplicationFiled: August 26, 2020Publication date: March 25, 2021Inventors: Horia C. Simionescu, Chung Kuang Chin, Paul Stonelake, Narasimhulu Dharanikumar Kotte
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Publication number: 20210089454Abstract: Systems and methods are disclosed including a first memory device, a second memory device coupled to the first memory device, where the second memory device has a lower access latency than the first memory device and acts as a cache for the first memory device. A processing device operatively coupled to the first and second memory devices can track access statistics of segments of data stored at the second memory device, the segments having a first granularity, and determine to update, based on the access statistics, a segment of data stored at the second memory device from the first granularity to a second granularity. The processing device can further retrieve additional data associated with the segment of data from the first memory device and store the additional data at the second memory device to form a new segment having the second granularity.Type: ApplicationFiled: August 26, 2020Publication date: March 25, 2021Inventors: Horia C. Simionescu, Paul Stonelake, Chung Kuang Chin, Narasimhulu Dharanikumar Kotte, Robert M. Walker, Cagdas Dirik
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Patent number: 10713163Abstract: A method of managing a solid state drive (SSD), comprising: storing a first set of data in a first plurality of non-volatile memory dies, the first plurality of non-volatile memory dies communicatively arranged in one or more first communication channels; storing a second set of data in a second plurality of non-volatile memory dies, the second plurality of non-volatile memory dies communicatively arranged in one or more second communication channels; generating a first set of system data corresponding only to the first set of data; generating a second set of system data corresponding only to the second set of data; and managing the first set of system data corresponding to the first set of data independently of the second set of system data corresponding to the second set of data, wherein the one or more first communication channel and the one or more second communication channel are communicatively coupled to one or more channel controllers, the one or more channel controls are communicatively coupled to aType: GrantFiled: September 11, 2018Date of Patent: July 14, 2020Assignee: Toshiba Memory CorporationInventors: Girish Desai, Narasimhulu DharaniKumar Kotte
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Publication number: 20200081834Abstract: A method of managing a solid state drive (SSD), comprising: storing a first set of data in a first plurality of non-volatile memory dies, the first plurality of non-volatile memory dies communicatively arranged in one or more first communication channels; storing a second set of data in a second plurality of non-volatile memory dies, the second plurality of non-volatile memory dies communicatively arranged in one or more second communication channels; generating a first set of system data corresponding only to the first set of data; generating a second set of system data corresponding only to the second set of data; and managing the first set of system data corresponding to the first set of data independently of the second set of system data corresponding to the second set of data, wherein the one or more first communication channel and the one or more second communication channel are communicatively coupled to one or more channel controllers, the one or more channel controls are communicatively coupled to aType: ApplicationFiled: September 11, 2018Publication date: March 12, 2020Inventors: Girish Desai, Narasimhulu DharaniKumar Kotte
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Patent number: 7206991Abstract: A mechanism is provided for migration between stripe storage and redundant parity striped storage. When a disk is added to a disk array, the mechanism migrates from RAID 0 to RAID 5. For each row, the mechanism calculates parity for the row and, if the parity position is not the new drive, the mechanism writes the data from the parity position to the new drive and writes the parity to the parity stripe position. If a drive fails, the mechanism migrates back from RAID 5 to RAID 0. For each row, if the parity position is not the failed drive, reads the data from remaining drives, XORs the data stripes to get failed drive data, and writes the failed drive data to the parity position. If a read or write is received for the failed drive, the mechanism simply redirects the read or write to the parity position.Type: GrantFiled: October 15, 2003Date of Patent: April 17, 2007Assignee: LSI Logic CorporationInventors: Paresh Chatterjee, Basavaraj Gurupadappa Hallyal, Senthil Murugan Thangaraj, Narasimhulu Dharanikumar Kotte, Ramya Subramanian