Abstract: One example method includes obtaining one or more histopathology images of a sample from a cancer patient; selecting a plurality of tissue image patches from the one or more histopathology images; determining, by a deep learning system comprising a plurality of trained machine learning (“ML”) models, a plurality of image features for the plurality of tissue image patch, wherein each tissue image patch is analyzed by one of the trained ML models; determining, by the deep learning system, probabilities of patient survival based on the determined plurality of image features; and generating, by the deep learning system, a prediction of patient survival based on the determined probabilities.

Abstract: One example method includes obtaining one or more histopathology images of a sample from a cancer patient; selecting a plurality of tissue image patches from the one or more histopathology images; determining, by a deep learning system comprising a plurality of trained machine learning (ML) models, a plurality of image features for the plurality of tissue image patch, wherein each tissue image patch is analyzed by one of the trained ML models; determining, by the deep learning system, probabilities of patient survival based on the determined plurality of image features; and generating, by the deep learning system, a prediction of patient survival based on the determined probabilities.

Abstract: An allocator assigns entries for a circular buffer. The allocator receives requests for storing data in entries of the circular buffer, and generates a head pointer to identify a starting entry in the circular buffer for which circular buffer entries are not allocated. In addition to pointing to an entry in the circular buffer, the head pointer includes a wrap bit. The allocator toggles the wrap bit each time the allocator traverses the linear queue of the circular buffer. A tail pointer is generated, including the wrap bit, to identify an ending entry in the circular buffer for which circular buffer entries are allocated. In response to the request for entries, the allocator sequentially assigns entries for the requests located between the head pointer and the tail pointer. The allocator has application for use in a microprocessor performing out-of-order dispatch anti speculative execution. The allocator is coupled to a reorder buffer, configured as a circular buffer, to permit allocation of entries.

Abstract: An allocator assigns entries for a circular buffer. The allocator receives requests for storing data in entries of the circular buffer, and generates a head pointer to identify a starting entry in the circular buffer for which circular buffer entries are not allocated. In addition to pointing to an entry in the circular buffer, the head pointer includes a wrap bit. The allocator toggles the wrap bit each time the allocator traverses the linear queue of the circular buffer. A tail pointer is generated, including the wrap bit, to identify an ending entry in the circular buffer for which circular buffer entries are allocated. In response to the request for entries, the allocator sequentially assigns entries for the requests located between the head pointer and the tail pointer. The allocator has application for use in a microprocessor performing out-of-order dispatch and speculative execution. The allocator is coupled to a reorder buffer, configured as a circular buffer, to permit allocation of entries.

Abstract: A carry-skip incrementor mitigating propagation delay experienced by conventional ripple carry incrementors without employing a substantially greater device count, includes a plurality of circuit blocks operating in combination with a plurality of logic gates. Each circuit block receives as input a varying number of data bits of an input operand and a carry signal and thereafter, generates a product signal and real bit sums corresponding to these data bits. The plurality of logic gates are arranged such that each logic gate receives as input the product signal from a first adjacent circuit block and the carry signal and outputs the carry signal for a second adjacent circuit block. The carry signal is active if the product signal and the carry signal are active. Thus, the delay associated with the first adjacent circuit block is bypassed in favor of the delay associated with the logic gate.

Abstract: A method and apparatus for handling resource allocation during processor stall conditions. The instruction issue components of a processor are stalled (e.g., the issuance of new instruction is frozen) as a result of various stall conditions. One stall condition (full stall) occurs when an allocated buffer resource becomes full. Another stall condition (partial stall) occurs during register renaming and a given instruction sources a larger register width than the register alias table currently contains within the RAT buffer. This is a partial width data dependency and a partial stall is asserted. The present invention, upon detection of a full stall, does not allocate any buffer entries within the clock cycle that causing the full stall and resource pointers are not advanced and instructions issued during that clock cycle are not allocated. Within the clock cycle of the deassertion of the full stall, the resource buffers are allocated and the resource allocation pointers are updated.