Abstract: Methods, systems, and computer-readable media for offline evaluation of machine learning models with noise reduction are disclosed. A trigger computation system generates a plurality of experimental requests. The experimental requests do not represent unmodified requests received from clients in a production environment. At least one parameter value varies for individual ones of the experimental requests. The trigger computation system provides the experimental requests to a first machine learning model and a second machine learning model. The first machine learning model and the second machine learning model produce a set of results based at least in part on the experimental requests. The trigger computation system determines a reduced set of results for which the first machine learning model and the second machine learning model differ. An evaluation of the first machine learning model or the second machine learning model is performed using the reduced set of results.

Abstract: One example method includes obtaining one or more histopathology images of a sample from a cancer patient; selecting a plurality of tissue image patches from the one or more histopathology images; determining, by a deep learning system comprising a plurality of trained machine learning (ML) models, a plurality of image features for the plurality of tissue image patch, wherein each tissue image patch is analyzed by one of the trained ML models; determining, by the deep learning system, probabilities of patient survival based on the determined plurality of image features; and generating, by the deep learning system, a prediction of patient survival based on the determined probabilities.

Abstract: Techniques are provided for managing airport slot reservations using a shared database network. A computing device receives information of one or more open airport slots. The availability of the open airport slots is validated through the shared database network and is stored in a shared ledger of the shared database network. The open airport slots are published to one or more carriers to initiate electronic transactions of the open airport slots. The computing device receives one or more bid transactions from the air carriers for the open airport slots. Each bid transaction has associated bid information. The bid transactions are validated using predefined validation rules, and they are allotted to corresponding open airport slots based on the predefined validation rules and the bid information. The bid transactions allocated to the corresponding open airport slots are published to the shared ledger.

Abstract: A method for providing circling approach data onboard an aircraft is disclosed. For a current, circling approach of the aircraft to a destination airport, the method identifies a circling approach procedure applicable to an optimal runway, by a processor communicatively coupled to a system memory element configured to store a database of circling approach procedures and a source for temporary restrictions; determines a circling boundary to the optimal runway, based on the circling approach procedure; determines temporary circling restrictions for the aircraft, based on conflicting traffic from at least a second airport; constructs a lateral path and a vertical path to guide the aircraft to the optimal runway of the destination airport, based on the circling approach procedure, the circling boundary, and the temporary circling restrictions; and presents graphical elements and text associated with the circling approach procedure, the circling boundary, and the temporary restrictions, by a display device.

Abstract: A system and method are provided that are directed to the technological problem of performing real-time trend analysis to provide real-time cockpit level event predictions. The provided systems and methods further provide real-time corrective action suggestions associated with the real-time trend analysis.

Abstract: An allocator assigns entries for a circular buffer. The allocator receives requests for storing data in entries of the circular buffer, and generates a head pointer to identify a starting entry in the circular buffer for which circular buffer entries are not allocated. In addition to pointing to an entry in the circular buffer, the head pointer includes a wrap bit. The allocator toggles the wrap bit each time the allocator traverses the linear queue of the circular buffer. A tail pointer is generated, including the wrap bit, to identify an ending entry in the circular buffer for which circular buffer entries are allocated. In response to the request for entries, the allocator sequentially assigns entries for the requests located between the head pointer and the tail pointer. The allocator has application for use in a microprocessor performing out-of-order dispatch anti speculative execution. The allocator is coupled to a reorder buffer, configured as a circular buffer, to permit allocation of entries.

Abstract: An allocator assigns entries for a circular buffer. The allocator receives requests for storing data in entries of the circular buffer, and generates a head pointer to identify a starting entry in the circular buffer for which circular buffer entries are not allocated. In addition to pointing to an entry in the circular buffer, the head pointer includes a wrap bit. The allocator toggles the wrap bit each time the allocator traverses the linear queue of the circular buffer. A tail pointer is generated, including the wrap bit, to identify an ending entry in the circular buffer for which circular buffer entries are allocated. In response to the request for entries, the allocator sequentially assigns entries for the requests located between the head pointer and the tail pointer. The allocator has application for use in a microprocessor performing out-of-order dispatch and speculative execution. The allocator is coupled to a reorder buffer, configured as a circular buffer, to permit allocation of entries.

Abstract: A carry-skip incrementor mitigating propagation delay experienced by conventional ripple carry incrementors without employing a substantially greater device count, includes a plurality of circuit blocks operating in combination with a plurality of logic gates. Each circuit block receives as input a varying number of data bits of an input operand and a carry signal and thereafter, generates a product signal and real bit sums corresponding to these data bits. The plurality of logic gates are arranged such that each logic gate receives as input the product signal from a first adjacent circuit block and the carry signal and outputs the carry signal for a second adjacent circuit block. The carry signal is active if the product signal and the carry signal are active. Thus, the delay associated with the first adjacent circuit block is bypassed in favor of the delay associated with the logic gate.

Abstract: A method and apparatus for handling resource allocation during processor stall conditions. The instruction issue components of a processor are stalled (e.g., the issuance of new instruction is frozen) as a result of various stall conditions. One stall condition (full stall) occurs when an allocated buffer resource becomes full. Another stall condition (partial stall) occurs during register renaming and a given instruction sources a larger register width than the register alias table currently contains within the RAT buffer. This is a partial width data dependency and a partial stall is asserted. The present invention, upon detection of a full stall, does not allocate any buffer entries within the clock cycle that causing the full stall and resource pointers are not advanced and instructions issued during that clock cycle are not allocated. Within the clock cycle of the deassertion of the full stall, the resource buffers are allocated and the resource allocation pointers are updated.