Patents by Inventor Narayan Kuddannavar

Narayan Kuddannavar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Scheme to reduce read disturb for high read intensive blocks in non-volatile memory
    Patent number: 10734084
    Abstract: A non-volatile storage system comprises non-volatile memory cells arranged in physical blocks, and one or more control circuits in communication with the non-volatile memory cells. The one or more control circuits are configured to write data to a physical block of the non-volatile memory cells with a scheme to reduce read disturb if a logical block associated with the physical block has a read intensity greater than a threshold.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: August 4, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Narayan Kuddannavar, Swaroop Kaza, Sainath Viswasarai
  • SCHEME TO REDUCE READ DISTURB FOR HIGH READ INTENSIVE BLOCKS IN NON-VOLATILE MEMORY
    Publication number: 20190371416
    Abstract: A non-volatile storage system comprises non-volatile memory cells arranged in physical blocks, and one or more control circuits in communication with the non-volatile memory cells. The one or more control circuits are configured to write data to a physical block of the non-volatile memory cells with a scheme to reduce read disturb if a logical block associated with the physical block has a read intensity greater than a threshold.
    Type: Application
    Filed: May 31, 2019
    Publication date: December 5, 2019
    Applicant: Western Digital Technologies, Inc.
    Inventors: Narayan Kuddannavar, Swaroop Kaza, Sainath Viswasarai