Abstract: A method of coding a ROM from a partially processed semiconductor wafer comprising a substrate, a plurality of spaced regions separated by regions of isolating oxide deposited in said substrate, a layer of gate oxide overlying each of said spaced regions and a gate electrode overlying each layer of said gate oxide, is described comprising the use of photoresist material for preventing the formation of source and drain regions under selected ones of said gate electrodes during a subsequent doping step. The photoresist material restricts the area of implantation of dopant used for forming source and drain regions in the ROM device.

Abstract: A method of fabricating CMOS integrated circuits including the ordered steps of: depositing a layer of phosphorus doped silicon oxide; heating the oxide layer at a temperature and duration sufficient to reflow and densify it; forming contact apertures in the oxide layer for exposing source and drain regions of transistors; and cleaning the wafer in an etchant solution for rounding off sharp edges on the oxide layer prior to contact metallization. In a preferred embodiment, all steps between forming contact apertures and through metallization are formed at a temperature that is lower than the temperature that will cause flow of the oxide layer.