Patents by Inventor Narayan Solayappan
Narayan Solayappan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100190288Abstract: Thin semiconductor foils can be formed using light reactive deposition. These foils can have an average thickness of less than 100 microns. In some embodiments, the semiconductor foils can have a large surface area, such as greater than about 900 square centimeters. The foil can be free standing or releasably held on one surface. The semiconductor foil can comprise elemental silicon, elemental germanium, silicon carbide, doped forms thereof, alloys thereof or mixtures thereof. The foils can be formed using a release layer that can release the foil after its deposition. The foils can be patterned, cut and processed in other ways for the formation of devices. Suitable devices that can be formed form the foils include, for example, photovoltaic modules and display control circuits.Type: ApplicationFiled: March 31, 2010Publication date: July 29, 2010Inventors: Henry Hieslmair, Ronald J. Mosso, Robert B. Lynch, Shivkumar Chiruvolu, William E. McGovern, Craig R. Horne, Narayan Solayappan, Ronald M. Cornell
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Publication number: 20090017292Abstract: Sub-atmospheric pressure chemical vapor deposition is described with a directed reactant flow and a substrate that moves relative to the flow. Thus, using this CVD configuration a relatively high deposition rate can be achieved while obtaining desired levels of coating uniformity. Deposition approaches are described to place one or more inorganic layers onto a release layer, such as a porous, particulate release layer. In some embodiments, the release layer is formed from a dispersion of submicron particles that are coated onto a substrate. The processes described can be effective for the formation of silicon films that can be separated with the use of a release layer into a silicon foil. The silicon foils can be used for the formation of a range of semiconductor based devices, such as display circuits or solar cells.Type: ApplicationFiled: June 12, 2008Publication date: January 15, 2009Inventors: Henry Hieslmair, Ronald J. Mosso, Narayan Solayappan, Shivkumar Chiruvolu, Julio E. Morris
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Patent number: 7459318Abstract: A three-dimensional (“3-D”) memory capacitor comprises a bottom electrode, a ferroelectric thin film, and a top electrode that conform to a 3-D surface of an insulator layer. The capacitance area is greater than the horizontal footprint area of the capacitor. Preferably, the footprint of the capacitor is less than 0.2 nm2, and the corresponding capacitance area is typically in a range of from 0.4 nm2 to 1.0 nm2 The ferroelectric thin film preferably has a thickness not exceeding 60 nm. A capacitor laminate including the bottom electrode, ferroelectric thin film, and the top electrode preferably has a thickness not exceeding 200 nm. A low-thermal-budget MOCVD method for depositing a ferroelectric thin film having a thickness in a range of from 30 nm to 90 nm includes an RTP treatment before depositing the top electrode and an RTP treatment after depositing the top electrode and etching the ferroelectric layer.Type: GrantFiled: April 26, 2006Date of Patent: December 2, 2008Assignee: Symetrix CorporationInventors: Carlos A. Paz de Araujo, Larry D. McMillan, Narayan Solayappan, Vikram Joshi
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Publication number: 20070212510Abstract: Thin semiconductor foils can be formed using light reactive deposition. These foils can have an average thickness of less than 100 microns. In some embodiments, the semiconductor foils can have a large surface area, such as greater than about 900 square centimeters. The foil can be free standing or releasably held on one surface. The semiconductor foil can comprise elemental silicon, elemental germanium, silicon carbide, doped forms thereof, alloys thereof or mixtures thereof. The foils can be formed using a release layer that can release the foil after its deposition. The foils can be patterned, cut and processed in other ways for the formation of devices. Suitable devices that can be formed form the foils include, for example, photovoltaic modules and display control circuits.Type: ApplicationFiled: March 13, 2007Publication date: September 13, 2007Inventors: Henry Hieslmair, Ronald J. Mosso, Robert B. Lynch, Shivkumar Chiruvolu, William E. McGovern, Craig R. Horne, Narayan Solayappan, Ronald M. Cornell
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Patent number: 7187079Abstract: A nonconductive hydrogen barrier layer is deposited on a substrate and completely covers the surface area over a memory capacitor and a MOSFET switch of an integrated circuit memory cell. A portion of an insulator layer adjacent to the bottom electrode of a memory capacitor is removed by etching to form a moat region. A nonconductive oxygen barrier layer is deposited to cover the sidewall and bottom of the moat. The nonconductive oxygen barrier layer and a conductive diffusion barrier beneath the capacitor together provide a substantially continuous diffusion barrier between the capacitor and a switch. Also, the nonconductive hydrogen barrier layer, the nonconductive oxygen barrier, and the conductive diffusion barrier substantially completely envelop the capacitor, in particular a ferroelectric thin film in the capacitor.Type: GrantFiled: September 19, 2003Date of Patent: March 6, 2007Assignee: Symetrix CorporationInventors: Vikram Joshi, Narayan Solayappan, Carlos A. Paz de Araujo, Larry D. McMillan
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Publication number: 20060194348Abstract: A three-dimensional (“3-D”) memory capacitor comprises a bottom electrode, a ferroelectric thin film, and a top electrode that conform to a 3-D surface of an insulator layer. The capacitance area is greater than the horizontal footprint area of the capacitor. Preferably, the footprint of the capacitor is less than 0.2 nm2, and the corresponding capacitance area is typically in a range of from 0.4 nm2 to 1.0 nm2 The ferroelectric thin film preferably has a thickness not exceeding 60 nm. A capacitor laminate including the bottom electrode, ferroelectric thin film, and the top electrode preferably has a thickness not exceeding 200 nm. A low-thermal-budget MOCVD method for depositing a ferroelectric thin film having a thickness in a range of from 30 nm to 90 nm includes an RTP treatment before depositing the top electrode and an RTP treatment after depositing the top electrode and etching the ferroelectric layer.Type: ApplicationFiled: April 26, 2006Publication date: August 31, 2006Applicant: Symetrix CorporationInventors: Carlos Araujo, Larry McMillan, Narayan Solayappan, Vikram Joshi
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Patent number: 7075134Abstract: A three-dimensional (“3-D”) memory capacitor comprises a bottom electrode, a ferroelectric thin film, and a top electrode that conform to a 3-D surface of an insulator layer. The capacitance area is greater than the horizontal footprint area of the capacitor. Preferably, the footprint of the capacitor is less than 0.2 nm2, and the corresponding capacitance area is typically in a range of from 0.4 nm2 to 1.0 nm2 The ferroelectric thin film preferably has a thickness not exceeding 60 nm. A capacitor laminate including the bottom electrode, ferroelectric thin film, and the top electrode preferably has a thickness not exceeding 200 nm. A low-thermal-budget MOCVD method for depositing a ferroelectric thin film having a thickness in a range of from 30 nm to 90 nm includes an RTP treatment before depositing the top electrode and an RTP treatment after depositing the top electrode and etching the ferroelectric layer.Type: GrantFiled: July 24, 2003Date of Patent: July 11, 2006Assignee: Symetrix CorporationInventors: Carlos A. Paz de Araujo, Larry D. McMillan, Narayan Solayappan, Vikram Joshi
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Patent number: 7064374Abstract: A hydrogen diffusion barrier in an integrated circuit is located to inhibit diffusion of hydrogen to a thin film of a metal oxide, such as a ferroelectric layered superlattice material, in an integrated circuit. The hydrogen diffusion barrier comprises at least one of the following chemical compounds: strontium tantalate, bismuth tantalate, tantalum oxide, titanium oxide, zirconium oxide and aluminum oxide. The hydrogen barrier layer is amorphous and is made by a MOCVD process at a temperature of 450° C. or less. A supplemental hydrogen barrier layer comprising a material selected from the group consisting of silicon nitride and a crystalline form of one of said hydrogen barrier layer materials is formed adjacent to said hydrogen diffusion barrier.Type: GrantFiled: June 21, 2004Date of Patent: June 20, 2006Assignee: Symetrix CorporationInventors: Narayan Solayappan, Jolanta Celinska, Vikram Joshi, Carlos A. Paz de Araujo, Larry D. McMillan
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Publication number: 20050094457Abstract: A ferroelectric memory includes a group of memory cells, each cell having a ferroelectric memory element, a drive line on which a voltage for writing information to the group of memory cells is placed, and a bit line on which information to be read out of the group of memory cells is placed. The memory is read by placing a voltage less than the coercive voltage of the ferroelectric memory element across a memory element. A preamplifier is connected between the memory cells and the bit line. A set switch is connected between the drive line and the memory cells, and a reset switch is connected to the memory cells in parallel with the preamplifier. Prior to reading, noise from the group of cells is discharged by grounding both electrodes of the ferroelectric memory element.Type: ApplicationFiled: April 28, 2003Publication date: May 5, 2005Applicant: Symetrix CorporationInventors: Zheng Chen, Vikram Joshi, Narayan Solayappan, Carlos Paz de Araujo, Larry McMillan
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Patent number: 6867452Abstract: A high dielectric constant insulator including a thin film of a metal oxide selected from the group consisting of tungsten-bronze-type oxides, pyrochlore-type oxides, and combinations of Bi2O3 with an oxide selected from the group consisting of perovskites and pyrochlore-type oxides. An embodiment contains metal oxides represented by the general stoichiometric formulas AB2O6, A2B2O7 and A2Bi2B2O10, wherein A represents A-site atoms selected from the group of metals consisting of Ba, Bi, Sr, Pb, Ca, K, Na and La; and B represents B-site atoms selected from the group of metals consisting of Ti, Zr, Ta, Hf, Mo, W and Nb. Preferably, the metal oxides are (BaxSr1?x)(TayNb1?y)2O6, where 0?y?1.0 and 0?y?1.0; (BaxSr1?x)2(TayNb1?y)2O7, where 0?x?1.0 and 0?y?1.0; and (BaxSr1?x)2Bi2(TayNb1?y)2O10, where 0?x?1.0 and 0?y?1.0. Thin films according to the invention have a relative dielectric constant ?40, and preferably about 100. The value of Vcc in the metal oxides of the invention is close to zero.Type: GrantFiled: October 23, 2002Date of Patent: March 15, 2005Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.Inventors: Shinichiro Hayashi, Vikram Joshi, Narayan Solayappan, Joseph D. Cuchiaro, Carlos A. Paz de Araujo
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Patent number: 6831313Abstract: A ferroelectric memory (436) includes a plurality of memory cells (73, 82, 100) each containing a ferroelectric thin film (15) including a microscopically composite material having a ferroelectric component (18) and a dielectric component (19), the dielectric component being a different chemical compound than the ferroelectric component. The dielectric component is preferably a fluxor, i.e., a material having a higher crystallization velocity than the ferroelectric component. The addition of the fluxor permits a ferroelectric thin film to be crystallized at a temperature of between 400° C. and 550° C.Type: GrantFiled: July 22, 2003Date of Patent: December 14, 2004Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoshi Uchiyama, Carlos A. Paz de Araujo, Vikram Joshi, Narayan Solayappan, Jolanta Celinska, Larry D. McMillan
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Publication number: 20040232468Abstract: A hydrogen diffusion barrier in an integrated circuit is located to inhibit diffusion of hydrogen to a thin film of a metal oxide, such as a ferroelectric layered superlattice material, in an integrated circuit. The hydrogen diffusion barrier comprises at least one of the following chemical compounds: strontium tantalate, bismuth tantalate, tantalum oxide, titanium oxide, zirconium oxide and aluminum oxide. The hydrogen barrier layer is amorphous and is made by a MOCVD process at a temperature of 450° C. or less. A supplemental hydrogen barrier layer comprising a material selected from the group consisting of silicon nitride and a crystalline form of one of said hydrogen barrier layer materials is formed adjacent to said hydrogen diffusion barrier.Type: ApplicationFiled: June 21, 2004Publication date: November 25, 2004Applicant: Symetrix CorporationInventors: Narayan Solayappan, Jolanta Celinska, Vikram Joshi, Carlos A. Paz de Araujo, Larry D. McMillan
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Patent number: 6815223Abstract: A precursor for forming a thin film of layered superlattice material is applied to an integrated circuit substrate. The precursor coating is heated using rapid thermal processing (RTP) with a ramping rate of 100° C./second at a hold temperature in a range of from 500° C. to 900° C. for a cumulative heating time not exceeding 30 minutes, and preferably less than 5 minutes. In fabricating a ferroelectric memory cell, the coating is heated in oxygen using RTP, then a top electrode layer is formed, and then the substrate including the coating is heated using RTP in oxygen or in nonreactive gas after forming the top electrode layer. The thin film of layered superlattice material preferably comprises strontium bismuth tantalate or strontium bismuth tantalum niobate, and preferably has a thickness in a range of from 25 nm to 120 nm. The process of fabricating a thin film of layered superlattice material typically has a thermal budget value not exceeding 960,000° C.Type: GrantFiled: November 22, 2002Date of Patent: November 9, 2004Assignee: Symetrix CorporationInventors: Jolanta Celinska, Vikram Joshi, Narayan Solayappan, Myoungho Lim, Larry D. McMillan, Carlos A. Paz de Araujo
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Publication number: 20040211998Abstract: An integrated circuit includes a layered superlattice material including one or more of the elements cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium. These elements may either be A-site elements or superlattice generator elements in the layered superlattice material. In one embodiment, one or more of these elements substitute for bismuth in a bismuth layered material. They also are preferably used in combination with one or more of the following elements: strontium, calcium, barium, bismuth, cadmium, lead, titanium, tantalum, hafnium, tungsten, niobium, zirconium, bismuth, scandium, yttrium, lanthanum, antimony, chromium, thallium, oxygen, chlorine, and fluorine. Some of these materials are ferroelectrics that crystallize at relatively low temperatures and are applied in ferroelectric non-volatile memories.Type: ApplicationFiled: May 20, 2004Publication date: October 28, 2004Applicant: Symetrix CorporationInventors: Carlos A. Paz de Araujo, Larry D. McMillan, Narayan Solayappan
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Patent number: 6787181Abstract: A method of forming a Bi-layered superlattice material on a substrate using chemical vapor deposition of a precursor solution of trimethylbismuth and a metal compound dissolved in an organic solvent. The precursor solution is heated and vaporized prior to deposition of the precursor solution on an integrated circuit substrate by chemical vapor deposition. No heating steps including a temperature of 650° C. or higher are used.Type: GrantFiled: October 26, 2001Date of Patent: September 7, 2004Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoshi Uchiyama, Narayan Solayappan, Carlos A. Paz de Araujo
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Patent number: 6781184Abstract: A hydrogen diffusion barrier in an integrated circuit is located to inhibit diffusion of hydrogen to a thin film of a metal oxide, such as a ferroelectric layered superlattice material, in an integrated circuit. The hydrogen diffusion barrier comprises at least one of the following chemical compounds: strontium tantalate, bismuth tantalate, tantalum oxide, titanium oxide, zirconium oxide and aluminum oxide. The hydrogen barrier layer is amorphous and is made by a MOCVD process at a temperature of 450° C. or less. A supplemental hydrogen barrier layer comprising a material selected from the group consisting of silicon nitride and a crystalline form of one of said hydrogen barrier layer materials is formed adjacent to said hydrogen diffusion barrier.Type: GrantFiled: November 29, 2001Date of Patent: August 24, 2004Assignee: Symetrix CorporationInventors: Narayan Solayappan, Jolanta Celinska, Vikram Joshi, Carlos A. Paz de Araujo, Larry D. McMillan
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Publication number: 20040129987Abstract: A ferroelectric memory (436) includes a plurality of memory cells (73, 82, 100) each containing a ferroelectric thin film (15) including a microscopically composite material having a ferroelectric component (18) and a dielectric component (19), the dielectric component being a different chemical compound than the ferroelectric component. The dielectric component is preferably a fluxor, i.e., a material having a higher crystallization velocity than the ferroelectric component. The addition of the fluxor permits a ferroelectric thin film to be crystallized at a temperature of between 400° C. and 550° C.Type: ApplicationFiled: July 22, 2003Publication date: July 8, 2004Inventors: Kiyoshi Uchiyama, Carlos A. Paz de Araujo, Vikram Joshi, Narayan Solayappan, Jolanta Celinska, Larry D. McMillan
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Publication number: 20040129961Abstract: A three-dimensional (“3-D”) memory capacitor comprises a bottom electrode, a ferroelectric thin film, and a top electrode that conform to a 3-D surface of an insulator layer. The capacitance area is greater than the horizontal footprint area of the capacitor. Preferably, the footprint of the capacitor is less than 0.2 nm2, and the corresponding capacitance area is typically in a range of from 0.4 nm2 to 1.0 nm2 The ferroelectric thin film preferably has a thickness not exceeding 60 nm. A capacitor laminate including the bottom electrode, ferroelectric thin film, and the top electrode preferably has a thickness not exceeding 200 nm. A low-thermal-budget MOCVD method for depositing a ferroelectric thin film having a thickness in a range of from 30 nm to 90 nm includes an RTP treatment before depositing the top electrode and an RTP treatment after depositing the top electrode and etching the ferroelectric layer.Type: ApplicationFiled: July 24, 2003Publication date: July 8, 2004Applicant: Symetrix CorporationInventors: Carlos A. Paz de Araujo, Larry D. McMillan, Narayan Solayappan, Vikram Joshi
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Patent number: 6743643Abstract: A nonconductive hydrogen barrier layer is deposited on a substrate and completely covers the surface area over a memory capacitor and a MOSFET switch of an integrated circuit memory cell. A portion of an insulator layer adjacent to the bottom electrode of a memory capacitor is removed by etching to form a moat region. A nonconductive oxygen barrier layer is deposited to cover the sidewall and bottom of the moat. The nonconductive oxygen barrier layer and a conductive diffusion barrier beneath the capacitor together provide a substantially continuous diffusion barrier between the capacitor and a switch. Also, the nonconductive hydrogen barrier layer, the nonconductive oxygen barrier, and the conductive diffusion barrier substantially completely envelop the capacitor, in particular a ferroelectric thin film in the capacitor.Type: GrantFiled: January 22, 2003Date of Patent: June 1, 2004Assignee: Symetrix CorporationInventors: Vikram Joshi, Narayan Solayappan, Carlos A. Paz de Araujo, Larry D. McMillan
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Publication number: 20040101977Abstract: A precursor for forming a thin film of layered superlattice material is applied to an integrated circuit substrate. The precursor coating is heated using rapid thermal processing (RTP) with a ramping rate of 100° C./second at a hold temperature in a range of from 500° C. to 900° C. for a cumulative heating time not exceeding 30 minutes, and preferably less than 5 minutes. In fabricating a ferroelectric memory cell, the coating is heated in oxygen using RTP, then a top electrode layer is formed, and then the substrate including the coating is heated using RTP in oxygen or in nonreactive gas after forming the top electrode layer. The thin film of layered superlattice material preferably comprises strontium bismuth tantalate or strontium bismuth tantalum niobate, and preferably has a thickness in a range of from 25 nm to 120 nm. The process of fabricating a thin film of layered superlattice material typically has a thermal budget value not exceeding 960,000° C.Type: ApplicationFiled: November 22, 2002Publication date: May 27, 2004Applicant: Symetrix CorporationInventors: Jolanta Celinska, Vikram Joshi, Narayan Solayappan, Myoungho Lim, Larry D. McMillan, Carlos A. Paz de Araujo