Patents by Inventor Narayana Rao VEDULA

Narayana Rao VEDULA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Read only memory array architecture and methods of operation
    Patent number: 9286997
    Abstract: An encoded ROM array structure couples a first one of a first set of bitlines to a second one of a second set of bitlines through a transistor when the wordline connected to the gate terminal of that transistor is asserted. This encoded arrangement can be extended to any number of encoded bitlines, e.g., 2, 4, 8, 16, and so on. Each of the first plurality and second sets of bit lines are coupled to circuits for charging and discharging the bitlines. To read data from the first set of bit lines, the second set of bitlines is discharged, and vice versa.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: March 15, 2016
    Assignee: Broadcom Corporation
    Inventors: Narayana Rao Vedula, Dechang Sun, Myron Buer
  • Read Only Memory Array Architecture and Methods of Operation
    Publication number: 20140268986
    Abstract: An encoded ROM array structure couples a first one of a first set of bitlines to a second one of a second set of bitlines through a transistor when the wordline connected to the gate terminal of that transistor is asserted. This encoded arrangement can be extended to any number of encoded bitlines, e.g., 2, 4, 8, 16, and so on. Each of the first plurality and second sets of bit lines are coupled to circuits for charging and discharging the bitlines. To read data from the first set of bit lines, the second set of bitlines is discharged, and vice versa.
    Type: Application
    Filed: March 27, 2013
    Publication date: September 18, 2014
    Inventors: Narayana Rao VEDULA, Dechang Sun, Myron Buer