Patents by Inventor Narayana Sri Harsha Gade

Narayana Sri Harsha Gade has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220210056
    Abstract: A computer-based method and system for synthesizing a Network-on-Chip (NoC) is provided. One method includes determining physical data, device data, bridge data, traffic data and domain data based on an input specification for the NoC; assigning a domain to each bridge port; partitioning each traffic flow into one of a plurality of bins based on the bridge port domain assignments and the domain crossing constraints; creating a virtual node at each bridge port endpoint; generating a candidate topology for each bin based on the physical data, the device data, the bridge data, the traffic data, the domain data and the virtual nodes, each candidate topology including bridge ports, a tree of routers, routes and connections; and generating a final topology by merging the candidate topologies.
    Type: Application
    Filed: March 16, 2022
    Publication date: June 30, 2022
    Applicant: Arm Limited
    Inventors: Nitin Kumar Agarwal, Anup Gangwar, Honnahuggi Harinath Venkata Naga Ambica Prasad, Ravishankar Sreedharan, Narayana Sri Harsha Gade
  • Patent number: 11329690
    Abstract: The present disclosure provides computer-based methods and a system for synthesizing a NoC that advantageously generate balanced NoC topologies without end-to-end fairness or local credit-based arbitration, and improve NoC performance when destination device bridge ports support only one incoming physical link per channel. More particularly, a clock domain is assigned to certain routers that satisfies the minimum frequency for the router while reducing clock domain transitions to neighboring routers, and the traffic flows received by these routers are balanced based on the traffic flow packet rates.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: May 10, 2022
    Assignee: Arm Limited
    Inventors: Narayana Sri Harsha Gade, Honnahuggi Harinath Venkata Naga Ambica Prasad, Anup Gangwar, Nitin Kumar Agarwal, Ravishankar Sreedharan
  • Patent number: 11310169
    Abstract: The present disclosure provides a computer-based method and system for synthesizing a NoC. Traffic data is determined or received, and a baseline topology is generated or received. For each router in the baseline topology, a number of edge virtual channel (EVC) combinations is determined, the transmittablility of the traffic classes are determined, and, when the traffic classes are not transmittable, the router is identified. A traffic class affinity graph (TCAG) is generated for each identified router. Traffic class combinations are generated for the identified routers based on the TCAGs and EVC combinations. The traffic classes of the identified routers are merged based on the traffic class combinations. A final EVC combination for each identified router is determined based on the merged traffic classes. A final topology is generated based, at least in part, on the merged traffic classes and the final EVC combinations for the identified routers.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: April 19, 2022
    Assignee: Arm Limited
    Inventors: Honnahuggi Harinath Venkata Naga Ambica Prasad, Nitin Kumar Agarwal, Anup Gangwar, Narayana Sri Harsha Gade, Ravishankar Sreedharan
  • Patent number: 11283729
    Abstract: The present disclosure provides a computer-based method and system for synthesizing a Network-on-Chip (NoC). Physical data, device data, bridge data and traffic data are determined based on an input specification for the NoC. A virtual channel (VC) is assigned to each traffic flow to create a plurality of VC assignments. A topology is generated, based on the physical data, the device data, the bridge data, the traffic data and the VC assignments, which includes bridge ports, routers and connections. Final locations for relocatable NoC elements (e.g., routers, etc.) are determined based on NoC element energy values for the relocatable NoC elements, and protocol-level pipelines may be inserted into the connections based on a timing parameter.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: March 22, 2022
    Assignee: Arm Limited
    Inventors: Anup Gangwar, Nitin Kumar Agarwal, Honnahuggi Harinath Venkata Naga Ambica Prasad, Narayana Sri Harsha Gade, Ravishankar Sreedharan
  • Patent number: 11194950
    Abstract: The present disclosure provides a computer-based method and system for synthesizing a NoC. Physical data, device data, bridge data and traffic data are determined based on an input specification for the NoC. A virtual channel (VC) is assigned to each traffic flow. A head of line (HoL) conflict graph (HCG) is constructed based on the traffic data and the VC assignments. The HGC is modified based on bridge data and the traffic data to generate a modified HCG. A plurality of traffic graphs (TGs) are constructed based on the physical data, the bridge data, the traffic data and the modified HCG. A candidate topology is generated for each TG, which includes the bridge ports, routers and connections. The candidate topologies are merged to create a merged candidate topology, and the routers within the merged candidate topology are merged to generate a final topology for the NoC.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: December 7, 2021
    Assignee: Arm Limited
    Inventors: Nitin Kumar Agarwal, Anup Gangwar, Honnahuggi Harinath Venkata Naga Ambica Prasad, Ravishankar Sreedharan, Narayana Sri Harsha Gade
  • Publication number: 20210168038
    Abstract: The present disclosure provides computer-based methods and a system for synthesizing a NoC that advantageously generate balanced NoC topologies without end-to-end fairness or local credit-based arbitration, and improve NoC performance when destination device bridge ports support only one incoming physical link per channel. More particularly, a clock domain is assigned to certain routers that satisfies the minimum frequency for the router while reducing clock domain transitions to neighboring routers, and the traffic flows received by these routers are balanced based on the traffic flow packet rates.
    Type: Application
    Filed: February 9, 2021
    Publication date: June 3, 2021
    Applicant: Arm Limited
    Inventors: Narayana Sri Harsha Gade, Honnahuggi Harinath Venkata Naga Ambica Prasad, Anup Gangwar, Nitin Kumar Agarwal, Ravishankar Sreedharan
  • Publication number: 20210160194
    Abstract: The present disclosure provides a computer-based method and system for synthesizing a NoC. Traffic data is determined or received, and a baseline topology is generated or received. For each router in the baseline topology, a number of edge virtual channel (EVC) combinations is determined, the transmittablility of the traffic classes are determined, and, when the traffic classes are not transmittable, the router is identified. A traffic class affinity graph (TCAG) is generated for each identified router. Traffic class combinations are generated for the identified routers based on the TCAGs and EVC combinations. The traffic classes of the identified routers are merged based on the traffic class combinations. A final EVC combination for each identified router is determined based on the merged traffic classes. A final topology is generated based, at least in part, on the merged traffic classes and the final EVC combinations for the identified routers.
    Type: Application
    Filed: January 19, 2021
    Publication date: May 27, 2021
    Applicant: Arm Limited
    Inventors: Honnahuggi Harinath Venkata Naga Ambica Prasad, Nitin Kumar Agarwal, Anup Gangwar, Narayana Sri Harsha Gade, Ravishankar Sreedharan
  • Publication number: 20210058289
    Abstract: The present disclosure provides a computer-based method and system for synthesizing a Network-on-Chip (NoC). Physical data, device data, bridge data and traffic data are determined based on an input specification for the NoC. A virtual channel (VC) is assigned to each traffic flow to create a plurality of VC assignments. A topology is generated, based on the physical data, the device data, the bridge data, the traffic data and the VC assignments, which includes bridge ports, routers and connections. Final locations for relocatable NoC elements (e.g., routers, etc.) are determined based on NoC element energy values for the relocatable NoC elements, and protocol-level pipelines may be inserted into the connections based on a timing parameter.
    Type: Application
    Filed: November 10, 2020
    Publication date: February 25, 2021
    Applicant: Arm Limited
    Inventors: Anup Gangwar, Nitin Kumar Agarwal, Honnahuggi Harinath Venkata Naga Ambica Prasad, Narayana Sri Harsha Gade, Ravishankar Sreedharan
  • Publication number: 20210036967
    Abstract: The present disclosure provides a computer-based method and system for synthesizing a NoC. Physical data, device data, bridge data and traffic data are determined based on an input specification for the NoC. A virtual channel (VC) is assigned to each traffic flow. A head of line (HoL) conflict graph (HCG) is constructed based on the traffic data and the VC assignments. The HGC is modified based on bridge data and the traffic data to generate a modified HCG. A plurality of traffic graphs (TGs) are constructed based on the physical data, the bridge data, the traffic data and the modified HCG. A candidate topology is generated for each TG, which includes the bridge ports, routers and connections. The candidate topologies are merged to create a merged candidate topology, and the routers within the merged candidate topology are merged to generate a final topology for the NoC.
    Type: Application
    Filed: October 21, 2020
    Publication date: February 4, 2021
    Applicant: Arm Limited
    Inventors: Nitin Kumar Agarwal, Anup Gangwar, Honnahuggi Harinath Venkata Naga Ambica Prasad, Ravishankar Sreedharan, Narayana Sri Harsha Gade