Patents by Inventor Narayanan Ganapathy

Narayanan Ganapathy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7055152
    Abstract: A system and method of managing memory in a system area network that registers buffers for use by an application program to access hardware adapters. The system and method maintains a list of registered buffers so that the application program may perform more than one request using the buffer. De-registration of a buffer occurs only upon an explicit de-registration or free command or upon the receipt of a request to modify the properties of the buffer, or in some cases, following the use of garbage collection techniques.
    Type: Grant
    Filed: August 15, 2001
    Date of Patent: May 30, 2006
    Assignee: Microsoft Corporation
    Inventor: Narayanan Ganapathy
  • Patent number: 7024672
    Abstract: Methods, systems, and computer program products that, by defining a common interface, allow for a single implementation of operations common to both kernel mode and user mode processing, relative to a hardware adapter. Corresponding kernel mode and user mode implementations of the operations are provided. For a given process, a call to the common interface is mapped to the kernel mode implementation for kernel mode processes and to the user mode implementation for user mode processes. The mapping may be performed at runtime or may be static. The common operation may provide a user mode process direct access to a hardware adapter, such as for sending and receiving information, without switching to kernel mode. A kernel mode implementation for operations unique to kernel mode processing, such as specifying security parameters for the hardware adapter to enforce, or initiating and terminating communication through the hardware adapter, also may be provided.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: April 4, 2006
    Assignee: Microsoft Corporation
    Inventors: Robin L. Callender, Narayanan Ganapathy
  • Publication number: 20050102578
    Abstract: A system, method and interface for consistently capturing kernel resident information are provided. An operating system architecture includes user mode modules and kernel mode applications. A user mode module initiates a kernel mode information request through an application program interface identifying one or more process threads of interest. A kernel mode module captures information corresponding to standard kernel mode information and corresponding to the specifically identified process threads. The information is returned in a pre-allocated buffer.
    Type: Application
    Filed: November 12, 2003
    Publication date: May 12, 2005
    Inventors: Andrew Bliss, John Service, Narayanan Ganapathy, Neill Clift, Yi Meng
  • Publication number: 20040003137
    Abstract: Methods, systems, and computer program products that, by defining a common interface, allow for a single implementation of operations common to both kernel mode and user mode processing, relative to a hardware adapter. Corresponding kernel mode and user mode implementations of the operations are provided. For a given process, a call to the common interface is mapped to the kernel mode implementation for kernel mode processes and to the user mode implementation for user mode processes. The mapping may be performed at runtime or may be static. The common operation may provide a user mode process direct access to a hardware adapter, such as for sending and receiving information, without switching to kernel mode. A kernel mode implementation for operations unique to kernel mode processing, such as specifying security parameters for the hardware adapter to enforce, or initiating and terminating communication through the hardware adapter, also may be provided.
    Type: Application
    Filed: June 26, 2002
    Publication date: January 1, 2004
    Inventors: Robin L. Callender, Narayanan Ganapathy
  • Patent number: 6182089
    Abstract: A method, system and computer program product for dynamically allocating large memory pages of different sizes. Each process can select multiple page sizes. An algorithm referred to as a “Coalescing Daemon” is used to allocate large pages. “High water marks” are specified to the operating system. A high water mark is the maximum percentage of total system memory that the Coalescing Daemon coalesces for a given page size. The high water marks are used to allocate a number of free memory pages for each specified page size. Separate freelists are created and maintained for each page size. Each freelist comprises a linked list of data structures that represent free physical memory pages. A bitmap is set-up by the operating system to represent all memory available to processes. The bitmap is used for determining which memory pages are free during coalescing. The Coalescing Daemon allocates memory pages using a weak, mild and strong coalescing policy.
    Type: Grant
    Filed: September 23, 1997
    Date of Patent: January 30, 2001
    Assignee: Silicon Graphics, Inc.
    Inventors: Narayanan Ganapathy, Luis F. Stevens, Curt F. Schimmel
  • Patent number: 6112285
    Abstract: A system, method and computer program product for virtual memory support for TLBs with multiple page sizes that require only minor revisions to existing operating system code and remains compatible with existing applications. The virtual memory support provided herein is transparent to many existing operating system procedures and application programs. Various page sizes such as 4 KB, 64 KB, 256 KB, 1 MB, 4 MB and 16 MB page sizes can be used by application programs and each process can use multiple page sizes. Base page sized PTEs and data structures associated with physical pages (PFDATs) are maintained. Maintaining PFDATs and PTEs at a base page level facilitates upgrading and downgrading of memory pages. In addition, different processes can have different views of the same data. Support is provided for upgrading and downgrading memory pages. Examples of operating system methods that can be used for virtual memory support for multiple page sized TLBs are provided herein.
    Type: Grant
    Filed: September 23, 1997
    Date of Patent: August 29, 2000
    Assignee: Silicon Graphics, Inc.
    Inventors: Narayanan Ganapathy, Luis F. Stevens, Curt F. Schimmel
  • Patent number: 6112286
    Abstract: A system, method and computer program product for reverse mapping a page of memory to one or more data structure references, such as page table entries, that reference the page of memory. A number m of fields of a page frame data structure are reserved for storing reverse mapping data for a page of memory. Each reserved field can store a reverse map entry for pointing to a data structure reference, such as a page table entry, that references the page of memory that is represented by the page frame data structure. Where a number n of references to the page of memory is greater than the number m of reserved fields, a reverse map table is generated for storing additional reverse map entries. When a reverse map table is generated, one of the reverse map entries in one of the reserved fields of the page frame data structure is moved to the reverse map table. A pointer to the reverse map table is placed in the now-vacant reserved field.
    Type: Grant
    Filed: September 19, 1997
    Date of Patent: August 29, 2000
    Assignee: Silicon Graphics, Inc.
    Inventors: Curt F. Schimmel, Narayanan Ganapathy, Bhanuprakash Subramanya, Luis Stevens