Abstract: The disclosure is related to systems and methods of providing superparity protection to data. A storage device or other processing system, such as a host, may be capable of providing intermediate superparity protection to data. For example, superparity may be determined in response to a command received at a storage device. A superparity can be determined for read data to provide superparity protection to the read data. It may also be determined whether the read data is already protected by a valid superparity.

Abstract: A design tool for generating circuit block constraints from a design environment. The design tool derives a fan-in cone function for each block input of a circuit block of a design. The fan-in cone function may include fan-in cone variables and block input variables. The fan-in cone functions are conjoined into a circuit block constraint functions. The circuit block constraint function is quantified to provide circuit block constraints. These constraints may be used in design verification (e.g. equivalence checking) and/or circuit analysis (e.g. timing rule generation).

Abstract: Embodiments of the present invention provide for a method and system for verifying that an implementation design is functionally equivalent to a predetermined functionality of a reference design where the reference and implementation designs may correspond to a portion of a larger integrated circuit design. The use of Symbolic Trajectory Evaluation (STE) to compare the designs may result in false failures. Therefore, one aspect of the present invention provides for comparing an expected result from the reference design to an actual result of the implementation design in order to determine a set of failure conditions. Constraints are then selectively applied to the set of failure conditions in an attempt to remove them. Another aspect of the present invention allows for the selective use of symbols rather than “X”s (unknowns) in order to avoid false failures due to certain inputs of the implementation design not being properly stimulated.

Abstract: A design tool for generating circuit block constraints from a design environment. The design tool derives a fan-in cone function for each block input of a circuit block of a design. The fan-in cone function may include fan-in cone variables and block input variables. The fan-in cone functions are conjoined into a circuit block constraint functions. The circuit block constraint function is quantified to provide circuit block constraints. These constraints may be used in design verification (e.g. equivalence checking) and/or circuit analysis (e.g. timing rule generation).

Abstract: Embodiments of the present invention provide for a method and system for verifying that an implementation design is functionally equivalent to a predetermined functionality of a reference design where the reference and implementation designs may correspond to a portion of a larger integrated circuit design. The use of Symbolic Trajectory Evaluation (STE) to compare the designs may result in false failures. Therefore, one aspect of the present invention provides for comparing an expected result from the reference design to an actual result of the implementation design in order to determine a set of failure conditions. Constraints are then selectively applied to the set of failure conditions in an attempt to remove them. Another aspect of the present invention allows for the selective use of symbols rather than “X”s (unknowns) in order to avoid false failures due to certain inputs of the implementation design not being properly stimulated.