Abstract: A method of retransmission packet combining at a receiver is disclosed. The method comprises determining, at the receiver, a noise level for a plurality of channels. A first signal is received comprising a packet. The receiver may attempt to decode the packet at the receiver, and send a request to a transmitting device to retransmit the packet when the attempt to decode the packet fails and the noise level for the plurality of channels is greater than a threshold level. The receiver can receive up to M retransmissions of the first signal comprising the packet, and combine the received first signal with one or more of the M received retransmissions of the first signal to form a combined signal. The packet in the combined signal can be decoded based on the combined signal.

Abstract: A partially manufactured semiconductor chip comprising a slice and a number of shells is a template for a communication and networking chip. The slice has a number of I/O ports, blocks, and PHYs. The hardmac PHYs are established to correspond to a high speed data transmission protocol. The interior of the template comprises logic gate arrays and configurable memory. Once particular protocols of data receipt and transmission are selected, the logic gate arrays and configurable memory can be programmed and otherwise configured to develop protocol layers for data networking and communication.

Abstract: A time division media access controller for use with a multi-port data switch and a method of controlling media access. In one embodiment, the time division media access controller includes a time division receive engine, a time division transmit engine and a time division arbiter coupled to the time division receive and transmit engines. The time division receive engine accepts data from a plurality of data ports and the time division transmit engine provides data to a plurality of data ports. The time division arbiter controls states of the time division receive and transmit engines based on throughput requirements of the data. In preferred embodiments, the time division media access controller complies with the IEEE 802.3 ethernet standard.

Abstract: A method synchronizes serial data stream output from a multiple-port system. The multiple-port system includes a plurality of port devices. The method includes (a) timing a serial data stream at each port device, the serial data stream including a series of data frames, (b) generating a framing signal at each port device, the framing signal indicating a boundary of the data frame in the serial data stream, (c) supplying the framing signal to a next port device, and (d) synchronizing, at each next port, the timing of the serial data stream in response to the supplied framing signal.

Abstract: A multiple port system includes a plurality of port devices, each port device including a control register set, and a control bus coupled to the plurality of port devices. The control bus provides a control signal to each port device, and the control signal includes port address information and register address information. The control register set includes a set of registers responsive to the control signal if the port address information indicates the corresponding port device, and a designated register responsive to the control signal if the port address information indicates one of the plurality of the port devices and the register address information indicates the designated register.

Abstract: A partially manufactured semiconductor chip comprising a slice and a number of shells is a template for a communication and networking chip. The slice has a number of I/O ports, blocks, and PHYs. The hardmac PHYs are established to correspond to a high speed data transmission protocol. The interior of the template comprises logic gate arrays and configurable memory. Once particular protocols of data receipt and transmission are selected, the logic gate arrays and configurable memory can be programmed and otherwise configured to develop protocol layers for data networking and communication.