Patents by Inventor Narayanan S. Iyer

Narayanan S. Iyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for shared cache coherency for a chip multiprocessor or multiprocessor system
    Patent number: 6976131
    Abstract: A method and apparatus for shared cache coherency for a chip multiprocessor or a multiprocessor system. In one embodiment, a multicore processor includes a plurality of processor cores, each having a private cache, and a shared cache. An internal snoop bus is coupled to each private cache and the shared cache to communicate data from each private cache to other private caches and the shared cache. In another embodiment, an apparatus includes a plurality of processor cores and a plurality of caches. One of the plurality of caches maintains cache lines in two different modified states. The first modified state indicates a most recent copy of a modified cache line, and the second modified state indicates a stale copy of the modified cache line.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: December 13, 2005
    Assignee: Intel Corporation
    Inventors: Vladimir Pentkovski, Vivek Garg, Narayanan S. Iyer, Jagannath Keshava
  • Method and apparatus for shared cache coherency for a chip multiprocessor or multiprocessor system
    Publication number: 20040039880
    Abstract: A method and apparatus for shared cache coherency for a chip multiprocessor or a multiprocessor system. In one embodiment, a multicore processor includes a plurality of processor cores, each having a private cache, and a shared cache. An internal snoop bus is coupled to each private cache and the shared cache to communicate data from each private cache to other private caches and the shared cache. In another embodiment, an apparatus includes a plurality of processor cores and a plurality of caches. One of the plurality of caches maintains cache lines in two different modified states. The first modified state indicates a most recent copy of a modified cache line, and the second modified state indicates a stale copy of the modified cache line.
    Type: Application
    Filed: August 23, 2002
    Publication date: February 26, 2004
    Inventors: Vladimir Pentkovski, Vivek Garg, Narayanan S. Iyer, Jagannath Keshava