Patents by Inventor Narayanan Terizhandur V

Narayanan Terizhandur V has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250089271
    Abstract: A memory device includes a stack of memory die packages. Each memory die package includes at least two memory dies. A switch is electrically coupled to at least one of the memory die packages. A bond wire electrically couples the switch to a substrate of the memory device. Each memory die is also electrically coupled to the switch. Based on a received control signal, the switch selects which memory die is electrically and/or communicatively coupled to the substrate using the electrical connections between the memory dies and the bond wire that electrically couples the switch to the substrate.
    Type: Application
    Filed: September 8, 2023
    Publication date: March 13, 2025
    Inventors: Nagesh Vodrahalli, Dmitry Vaysman, Md. Sayed Mobin, John Randall, Narayanan Terizhandur V
  • Publication number: 20240387461
    Abstract: A semiconductor device package includes a substrate and a stack of semiconductor dies positioned on the substrate that includes a first semiconductor die and a second semiconductor die. First and second platforms are positioned on the substrate such that the stack of semiconductor dies is positioned therebetween. First and second through-vias are electrically connected to the substrate and extending through the respective first and second platforms. A first bond wire electrically connects the first through-via to the first semiconductor die, and a second bond wire electrically connects the second through-via to the second semiconductor die. The through-vias may reduce the required length of the bond wires thereby reducing signal noise and the platforms may vertically space the bond wires from one another to prevent electrical short circuits.
    Type: Application
    Filed: August 7, 2023
    Publication date: November 21, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Rajitha Indla, Narayanan Terizhandur V, Nagesh Vodrahalli
  • Publication number: 20240312916
    Abstract: A semiconductor device package includes a substrate, a stack of memory dies positioned on the substrate, and an interposer spaced from the stack of memory dies and also positioned on the substrate. First and second sets of bond pads are electrically connected to the substrate, where the second set of bond pads is positioned on the interposer above the substrate. A first set of bond wires electrically connects a first sub-stack of the memory dies to the first set of bond pads. A second set of bond wires electrically connects a second sub-stack of memory dies, positioned above the first sub-stack, to the second set of bond wires. The first and second sub-stacks of memory dies may be electrically isolated from one another to reduce noise in electrical signals transmitted to and from the memory dies.
    Type: Application
    Filed: July 28, 2023
    Publication date: September 19, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Nagesh Vodrahalli, Chih-Yang Li, Shrikar Bhagath, Narayanan Terizhandur V
  • Publication number: 20240079318
    Abstract: A storage device includes a substrate of a memory package and a first memory die. The substrate includes a controller and a first pin pad, the first pin pad being electrically connected to the controller and defining a data channel for data communications. The first memory die includes a front pin pad electrically connected to the first pin pad of the substrate by way of a first bond wire, a rear pin pad, a redistribution layer electrically connecting the front pin pad and the rear pin pad of the first memory die, and a plurality of memory cells configured to provide non-volatile storage accessible by way of the data channel.
    Type: Application
    Filed: September 6, 2022
    Publication date: March 7, 2024
    Inventors: Md. Sayed Mobin, Nagesh Vodrahalli, Pranav Balachander, Narayanan Terizhandur V