Patents by Inventor Narendhiran CR

Narendhiran CR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11195820
    Abstract: A fractured semiconductor die is disclosed, together with a semiconductor device including the fractured semiconductor die. During fabrication of the semiconductor dies in a wafer, the wafer may be scored in a series of parallel scribe lines through portions of each row of semiconductor dies. The scribe lines then propagate through the full thickness of the wafer to fracture off a portion of each of the semiconductor dies. It may happen that electrical traces such as bit lines in the memory cell arrays short together during the die fracture process. These electrical shorts may be cleared by running a current through each of the electrical traces.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: December 7, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Daniel Linnen, Kirubakaran Periyannan, Jayavel Pachamuthu, Narendhiran Cr, Jay Dholakia, Everett Lyons, IV, Hoang Huynh, Dat Dinh
  • Patent number: 11188511
    Abstract: Systems and methods are disclosed for a self-indexing removable storage device. In certain embodiments, the removable storage device is configured to be connected to a memory reader of a host device. The removable storage device comprises storage media, a controller configured to run firmware, and a buffer. The controller is configured to, while connected to a first host device, receive a write operation from the first host device, monitor changes to the storage media caused by the write operation, and update a file index stored on the removable storage device with the monitored changes. The controller is further configured to, in response to connecting the removable storage device to a memory reader of a second host device, provide the file index to an application on the second host device, and cause the application to display files on the storage media based on the file index.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: November 30, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Narendhiran Cr, Muralitharan Jayaraman, Sivaraj Velusamy, Chandra Lakkimsetty, Vithya Kannappan, Balakumar Rajendran
  • Publication number: 20210326054
    Abstract: A storage system with privacy-centric multi-partitions and method for use therewith are provided. In one embodiment, a storage system comprises a memory configured to be partitioned into a plurality of partitions, wherein each partition is associated with its own boot block, and wherein each boot block is configured to boot any of the plurality of partitions. The storage system also comprises a controller configured to communicate with the memory and to: in response to a failure to boot one of the plurality of partitions with that partition's boot block, use a boot block of another one of the plurality of partitions to boot the one of the plurality of partitions; and restrict access to each of the plurality of partitions only to authenticated entities. Other embodiments are provided.
    Type: Application
    Filed: April 20, 2020
    Publication date: October 21, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Muralitharan Jayaraman, Mayur Jain, Balakumar Rajendran, Narendhiran CR, Garvita Chauhan, Prashantha Krishna
  • Patent number: 11139276
    Abstract: A fractured semiconductor die is disclosed, together with a semiconductor device including the fractured semiconductor die. During fabrication of the semiconductor dies in a wafer, the wafer may be scored in a series of parallel scribe lines through portions of each row of semiconductor dies. The scribe lines then propagate through the full thickness of the wafer to fracture off a portion of each of the semiconductor dies. It may happen that electrical traces such as bit lines in the memory cell arrays short together during the die fracture process. These electrical shorts may be cleared by running a current through each of the electrical traces.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: October 5, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Daniel Linnen, Kirubakaran Periyannan, Jayavel Pachamuthu, Narendhiran Cr, Jay Dholakia, Everett Lyons, IV, Hoang Huynh, Dat Dinh
  • Publication number: 20210280559
    Abstract: A fractured semiconductor die is disclosed, together with a semiconductor device including the fractured semiconductor die. During fabrication of the semiconductor dies in a wafer, the wafer may be scored in a series of parallel scribe lines through portions of each row of semiconductor dies. The scribe lines then propagate through the full thickness of the wafer to fracture off a portion of each of the semiconductor dies. It may happen that electrical traces such as bit lines in the memory cell arrays short together during the die fracture process. These electrical shorts may be cleared by running a current through each of the electrical traces.
    Type: Application
    Filed: March 3, 2020
    Publication date: September 9, 2021
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Daniel Linnen, Kirubakaran Periyannan, Jayavel Pachamuthu, Narendhiran CR, Jay Dholakia, Everett Lyons, IV, Hoang Huynh, Dat Dinh
  • Patent number: 11106518
    Abstract: A method for error correction in a memory system includes determining a bit error ratio for a memory block of the memory system during a read operation. The method further includes determining whether the bit error ratio is between a first threshold and a second threshold. The method further includes based on a determination that the bit error ratio is between the first threshold and the second threshold, performing a select gate drain (SGD) read operation on a SGD word line of the memory block. The method further includes generating first soft bit data using SGD data corresponding to the SGD read operation. The method further includes performing a low-density parity-check correction using the first soft bit data on the memory block.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: August 31, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Indu Kumari, Narendhiran CR, Abhinand Amarnath, Balakumar Rajendran, Muralitharan Jayaraman
  • Publication number: 20200387493
    Abstract: Systems and methods are disclosed for a self-indexing removable storage device. In certain embodiments, the removable storage device is configured to be connected to a memory reader of a host device. The removable storage device comprises storage media, a controller configured to run firmware, and a buffer. The controller is configured to, while connected to a first host device, receive a write operation from the first host device, monitor changes to the storage media caused by the write operation, and update a file index stored on the removable storage device with the monitored changes. The controller is further configured to, in response to connecting the removable storage device to a memory reader of a second host device, provide the file index to an application on the second host device, and cause the application to display files on the storage media based on the file index.
    Type: Application
    Filed: June 4, 2019
    Publication date: December 10, 2020
    Inventors: Narendhiran CR, Muralitharan Jayaraman, Sivaraj Velusamy, Chandra Lakkimsetty, Vithya Kannappan, Balakumar Rajendran
  • Publication number: 20200278896
    Abstract: A method for error correction in a memory system includes determining a bit error ratio for a memory block of the memory system during a read operation. The method further includes determining whether the bit error ratio is between a first threshold and a second threshold. The method further includes based on a determination that the bit error ratio is between the first threshold and the second threshold, performing a select gate drain (SGD) read operation on a SGD word line of the memory block. The method further includes generating first soft bit data using SGD data corresponding to the SGD read operation. The method further includes performing a low-density parity-check correction using the first soft bit data on the memory block.
    Type: Application
    Filed: March 1, 2019
    Publication date: September 3, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: Indu Kumari, Narendhiran CR, Abhinand Amarnath, Balakumar Rajendran, Muralitharan Jayaraman
  • Patent number: 10268387
    Abstract: Technology is described herein for performing memory array operations in multiple memory dies in parallel. The memory dies, or groups of non-volatile memory cells on the memory dies, may exhibit different performance times for memory array operations. For example, non-volatile memory cells on one memory die may program more slowly than those on another memory die. The performance times of the memory dies (or groups of the memory cells on different memory dies) may be characterized relative to one another. Memory dies having similar performance times may be placed into the same meta-groups. Meta-groups may be formed at the die, zone, or block level. The meta-groups can be re-formed over the lifetime of the memory system, which can account for changes in performance times over the lifetime of the memory system.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: April 23, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Narendhiran Cr, Satya Kesav Gundabathula, Muralitharan Jayaraman, Chittoor Devarajan Sunilkumar, Satrajit Chakraborty
  • Publication number: 20180188956
    Abstract: Technology is described herein for performing memory array operations in multiple memory dies in parallel. The memory dies, or groups of non-volatile memory cells on the memory dies, may exhibit different performance times for memory array operations. For example, non-volatile memory cells on one memory die may program more slowly than those on another memory die. The performance times of the memory dies (or groups of the memory cells on different memory dies) may be characterized relative to one another. Memory dies having similar performance times may be placed into the same meta-groups. Meta-groups may be formed at the die, zone, or block level. The meta-groups can be re-formed over the lifetime of the memory system, which can account for changes in performance times over the lifetime of the memory system.
    Type: Application
    Filed: January 4, 2017
    Publication date: July 5, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Narendhiran CR, Satya Kesav Gundabathula, Muralitharan Jayaraman, Chittoor Devarajan Sunilkumar, Satrajit Chakraborty