Patents by Inventor Narendra B. Devta-Prasanna
Narendra B. Devta-Prasanna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8819508Abstract: An integrated circuit comprises a decoder having a plurality of select signal outputs, a multiplexer having a plurality of select signal inputs subject to a specified select signal constraint, and scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells coupled between respective ones of the select signal outputs of the decoder and respective ones of the select signal inputs of the multiplexer. The scan test circuitry is configured to control at least a given one of the scan cells so as to prevent violation of the select signal constraint in conjunction with scan testing. The multiplexer may be, for example, a one-hot multiplexer for which the select signal constraint indicates that only one of the select signal inputs should receive a logic high select signal at a particular time.Type: GrantFiled: October 5, 2012Date of Patent: August 26, 2014Assignee: LSI CorporationInventors: Narendra B. Devta Prasanna, Ramesh C. Tekumalla
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Publication number: 20140101501Abstract: An integrated circuit comprises a decoder having a plurality of select signal outputs, a multiplexer having a plurality of select signal inputs subject to a specified select signal constraint, and scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells coupled between respective ones of the select signal outputs of the decoder and respective ones of the select signal inputs of the multiplexer. The scan test circuitry is configured to control at least a given one of the scan cells so as to prevent violation of the select signal constraint in conjunction with scan testing. The multiplexer may be, for example, a one-hot multiplexer for which the select signal constraint indicates that only one of the select signal inputs should receive a logic high select signal at a particular time.Type: ApplicationFiled: October 5, 2012Publication date: April 10, 2014Applicant: LSI CorporationInventors: Narendra B. Devta Prasanna, Ramesh C. Tekumalla
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Patent number: 8694951Abstract: An apparatus having a core and one or more logic blocks is disclosed. The core may be embedded within the apparatus. The core is generally (i) configured to perform a function and (ii) wrapped internally by a first scan chain before being embedded within the apparatus. The logic blocks may be (i) positioned external to the core and (ii) coupled to one or more parallel interfaces of the first scan chain. A second scan chain may be configured to wrap both the logic blocks and the core.Type: GrantFiled: October 2, 2012Date of Patent: April 8, 2014Assignee: LSI CorporationInventors: Narendra B. Devta Prasanna, Saket K. Goyal, Vankat Rajesh Atluri
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Publication number: 20140096097Abstract: An apparatus having a core and one or more logic blocks is disclosed. The core may be embedded within the apparatus. The core is generally (i) configured to perform a function and (ii) wrapped internally by a first scan chain before being embedded within the apparatus. The logic blocks may be (i) positioned external to the core and (ii) coupled to one or more parallel interfaces of the first scan chain. A second scan chain may be configured to wrap both the logic blocks and the core.Type: ApplicationFiled: October 2, 2012Publication date: April 3, 2014Applicant: LSI CORPORATIONInventors: Narendra B. Devta Prasanna, Saket K. Goyal, Vankat Rajesh Atluri
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Patent number: 8515695Abstract: A method and an apparatus for evaluating SDDC of a test pattern set are disclosed. In one embodiment, the method includes: (1) selecting a transition fault of an IC detected by a test pattern set, the transition fault occurring at a fault site of the IC, (2) identifying path delays of a longest testable path and a longest tested path of the IC, wherein both the longest testable path and the longest tested path include the fault site, (3) determining a SDD detection probability for both the longest testable path and the longest tested path based on a probability that a SDD will be detected if present at the fault site and (4) calculating SDDC for the transition fault by dividing the SDD detection probability of the longest tested path by the SDD detection probability of the longest testable path.Type: GrantFiled: April 9, 2009Date of Patent: August 20, 2013Assignee: LSI CorporationInventors: Narendra B. Devta-Prasanna, Sandeep Kumar Goel
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Patent number: 8412994Abstract: Clock control circuitry for an integrated circuit, a method of testing an integrated circuit having a clock gate, an integrated circuit and a library of cells including the clock control circuitry are provided. In one embodiment, the integrated circuit includes: (1) a clock gate configured to apply a clock signal to at least a first scan chain of the integrated circuit, (2) combinational logic coupled to an input of the clock gate and (3) Design-for-Test logic located external to the combinational logic and coupled to the clock gate and a first cell of a second scan chain of the integrated circuit, the Design-for-Test logic configured to control operation of the clock gate based on a logic value of the first cell.Type: GrantFiled: September 17, 2010Date of Patent: April 2, 2013Assignee: LSI CorporationInventor: Narendra B. Devta-Prasanna
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Patent number: 8352818Abstract: A method for generating a test pattern set for detecting small delay defects of an IC is disclosed. In one embodiment, the method includes: (1) generating a traditional delay fault pattern, (2) fault grading the traditional delay fault pattern for small delay defect coverage, (3) reporting faults detected by the fault grading and delay information associated with the detected faults, (4) determining which of the detected faults are timing-aware target faults employing the delay information and (5) generating timing-aware delay fault patterns for the timing-aware target faults.Type: GrantFiled: December 16, 2008Date of Patent: January 8, 2013Assignee: LSI CorporationInventors: Sandeep Kumar Goel, Narendra B. Devta-Prasanna, Ritesh P. Turakhia
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Publication number: 20120072797Abstract: Clock control circuitry for an integrated circuit, a method of testing an integrated circuit having a clock gate, an integrated circuit and a library of cells including the clock control circuitry are provided. In one embodiment, the integrated circuit includes: (1) a clock gate configured to apply a clock signal to at least a first scan chain of the integrated circuit, (2) combinational logic coupled to an input of the clock gate and (3) Design-for-Test logic located external to the combinational logic and coupled to the clock gate and a first cell of a second scan chain of the integrated circuit, the Design-for-Test logic configured to control operation of the clock gate based on a logic value of the first cell.Type: ApplicationFiled: September 17, 2010Publication date: March 22, 2012Applicant: LSI CorporationInventor: Narendra B. Devta-Prasanna
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Patent number: 8140923Abstract: The disclosure provides embodiments of ICs and a method of testing an IC. In one embodiment, an IC includes: (1) a functional logic path having a node and at least one sequential logic element and (2) test circuitry coupled to the functional logic path and having a delay block, the test circuitry configured to form a testable path including the delay block and the node in response to a test mode signal, wherein a delay value of the delay block is selected to detect a small delay defect associated with the node.Type: GrantFiled: April 9, 2009Date of Patent: March 20, 2012Assignee: LSI CorporationInventors: Sandeep Kumar Goel, Narendra B. Devta-Prasanna
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Publication number: 20100262876Abstract: The disclosure provides embodiments of ICs and a method of testing an IC. In one embodiment, an IC includes: (1) a functional logic path having a node and at least one sequential logic element and (2) test circuitry coupled to the functional logic path and having a delay block, the test circuitry configured to form a testable path including the delay block and the node in response to a test mode signal, wherein a delay value of the delay block is selected to detect a small delay defect associated with the node.Type: ApplicationFiled: April 9, 2009Publication date: October 14, 2010Applicant: LSI CorporationInventors: Sandeep Kumar Goel, Narendra B. Devta-Prasanna
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Publication number: 20100262394Abstract: A method and an apparatus for evaluating SDDC of a test pattern set are disclosed. In one embodiment, the method includes: (1) selecting a transition fault of an IC detected by a test pattern set, the transition fault occurring at a fault site of the IC, (2) identifying path delays of a longest testable path and a longest tested path of the IC, wherein both the longest testable path and the longest tested path include the fault site, (3) determining a SDD detection probability for both the longest testable path and the longest tested path based on a probability that a SDD will be detected if present at the fault site and (4) calculating SDDC for the transition fault by dividing the SDD detection probability of the longest tested path by the SDD detection probability of the longest testable path.Type: ApplicationFiled: April 9, 2009Publication date: October 14, 2010Applicant: LSI CorporationInventors: Narendra B. Devta-Prasanna, Sandeep Kumar Goel
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Publication number: 20100153795Abstract: A method for generating a test pattern set for detecting small delay defects of an IC is disclosed. In one embodiment, the method includes: (1) generating a traditional delay fault pattern, (2) fault grading the traditional delay fault pattern for small delay defect coverage, (3) reporting faults detected by the fault grading and delay information associated with the detected faults, (4) determining which of the detected faults are timing-aware target faults employing the delay information and (5) generating timing-aware delay fault patterns for the timing-aware target faults.Type: ApplicationFiled: December 16, 2008Publication date: June 17, 2010Applicant: LSI CorporationInventors: Sandeep Kumar Goel, Narendra B. Devta-Prasanna, Ritesh P. Turakhia