Patents by Inventor Narendra C. Nandam

Narendra C. Nandam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for inter-processor communication
    Patent number: 9256502
    Abstract: A system including a DCU with a DMS located on the first node, where the DMS is associated with an interrupt receive register. The system further includes a second DCU located on second node that includes a GMS located on the second node, where the GMS is associated with an interrupt dispatch register. The GMS is configured to identify the DMS, determine a payload to transmit to DMS, issue cross-calls using the interrupt dispatch register, where a cross-call is issued for each non-zero bit in the payload, and issue a cross-call including a completion vector. The DCU is configured to receive the cross-calls from the GMS, in response to each of the cross-calls, set a corresponding bit-location in the second interrupt receive register to one, and after receiving the completion vector, use a current state of the interrupt receive register to determine a physical address.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: February 9, 2016
    Assignee: Oracle International Corporation
    Inventors: Narendra C. Nandam, Vincent Paul Graham
  • METHOD AND SYSTEM FOR INTER-PROCESSOR COMMUNICATION
    Publication number: 20130339794
    Abstract: A system including a DCU with a DMS located on the first node, where the DMS is associated with an interrupt receive register. The system further includes a second DCU located on second node that includes a GMS located on the second node, where the GMS is associated with an interrupt dispatch register. The GMS is configured to identify the DMS, determine a payload to transmit to DMS, issue cross-calls using the interrupt dispatch register, where a cross-call is issued for each non-zero bit in the payload, and issue a cross-call including a completion vector. The DCU is configured to receive the cross-calls from the GMS, in response to each of the cross-calls, set a corresponding bit-location in the second interrupt receive register to one, and after receiving the completion vector, use a current state of the interrupt receive register to determine a physical address.
    Type: Application
    Filed: June 19, 2012
    Publication date: December 19, 2013
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventors: Narendra C. Nandam, Vincent Paul Graham