Abstract: A system and device for reducing instantaneous voltage droop (IVD) during a scan shift operation. In one embodiment, a system includes a first group of clock gating cells configured to receive an input clock signal and a first group of flip-flops coupled to the first group of clock gating cells. Each clock gating cell of the first group of clock gating cells includes a first delay element to delay the input clock signal by a first duration during a scan shift operation. The system also includes a second group of clock gating cells configured to receive the input clock signal, and a second group of flip-flops coupled to the second group of clock gating cells. Each clock gating cell of the second group of clock gating cells includes a second delay element to delay the input clock signal by a second duration during the scan shift operation.

Abstract: A system and device for reducing instantaneous voltage droop (IVD) during a scan shift operation is disclosed. In one embodiment, a system includes a first group of clock gating cells configured to receive an input clock signal and a first group of flip-flops coupled to the first group of clock gating cells. Each clock gating cell of the first group of clock gating cells includes a first delay element to delay the input clock signal by a first duration during a scan shift operation. The system also includes a second group of clock gating cells configured to receive the input clock signal, and a second group of flip-flops coupled to the second group of clock gating cells. Each clock gating cell of the second group of clock gating cells includes a second delay element to delay the input clock signal by a second duration during the scan shift operation.

Abstract: A logic built-in self-test (LBIST) module and a method of online system testing. In one embodiment, the LBIST module includes: (1) first and second data sources selectable to provide alternative respective first and second data to at least one scan chain and (2) a scan clock modifier associated with the first and second data sources and configured to drive the at least one scan chain with a selectively aperiodic modified scan clock signal.

Abstract: A method for implementing test generation for systematic scan reconfiguration in an integrated circuit is presented. The method may comprise: defining at least one set of detectable faults; setting an SAS decoder configuration, the SAS decoder configuration including a don't-care bit; generating an ATPG pattern; and applying the ATPG pattern to one or more scan chain segments having a segment address associated with the SAS decoder configuration.

Abstract: The present invention is directed to a system and method for quality improvement by identifying test patterns for DFT logic faults and functional logic faults. The identified test patterns may be selectively utilized for pruning of patterns or DPM estimation. Functional faults and DFT faults may be identified from detected TDF faults. The functional faults are faults on a logic which was present in a pre-test insertion net list. Remaining faults are the DFT faults. A set of test patterns for DFT faults may be utilized as the first target for the pattern truncation which will reduce the amount of test patterns to be tested. A set of test patterns for functional may be utilized for improving the TDF coverage.

Abstract: The present invention is directed to a system and method for improving transition delay test coverage through use of enhanced flip flops (ES flip-flops) for a broadside test approach. Each ES flip-flop includes a two port flip-flop including a first flip-flop and a second flip-flop. A separate control input (ESM) which is not time critical is used to select a multiplexer of the second flip-flop. Thus, the ES flip-flops do not require a fast signal switching between launch and test response capture or an extra clock signal. Various enhanced scan modes may be selected via a combination of SEN and ESM. Moreover, only a heuristically selected subset of scan flip-flops may be replaced with the ES flip-flops so as to minimize the length of a scan chain as well as the logic area overhead. The present invention provides high TDF coverage under the broadside testing.

Abstract: The present invention is directed to a system and method for improving transition delay fault coverage through use of augmented flip-flops (TL flops) for a broadside test approach. The TL flops use the same clock for scan and functional operation. Thus, the TL flops do not require a fast signal switching between launch and test response capture. Each of the TL flops includes additional multiplexer in front of a standard scan flop and a transition enable (TEN) signal. Moreover, only a heuristically selected subset of scan flip-flops is replaced with the TL flops and only one additional MUX per selected scan flip-flop may contribute an area overhead. Consequently, the overall chip area overhead may be minimal. The present invention may be suitable for being implemented with currently available third party ATPG.

Abstract: The present invention is directed to a system and method for quality improvement by identifying test patterns for DFT logic faults and functional logic faults. The identified test patterns may be selectively utilized for pruning of patterns or DPM estimation. Functional faults and DFT faults may be identified from detected TDF faults. The functional faults are faults on a logic which was present in a pre-test insertion net list. Remaining faults are the DFT faults. A set of test patterns for DFT faults may be utilized as the first target for the pattern truncation which will reduce the amount of test patterns to be tested. A set of test patterns for functional may be utilized for improving the TDF coverage.

Abstract: The present invention is directed to a system and method for improving transition delay test coverage through use of enhanced flip flops (ES flip-flops) for a broadside test approach. Each ES flip-flop includes a two port flip-flop including a first flip-flop and a second flip-flop. A separate control input (ESM) which is not time critical is used to select a multiplexer of the second flip-flop. Thus, the ES flip-flops do not require a fast signal switching between launch and test response capture or an extra clock signal. Various enhanced scan modes may be selected via a combination of SEN and ESM. Moreover, only a heuristically selected subset of scan flip-flops may be replaced with the ES flip-flops so as to minimize the length of a scan chain as well as the logic area overhead. The present invention provides high TDF coverage under the broadside testing.

Abstract: The present invention is directed to a system and method for improving transition delay fault coverage through use of augmented flip-flops (TL flops) for a broadside test approach. The TL flops use the same clock for scan and functional operation. Thus, the TL flops do not require a fast signal switching between launch and test response capture. Each of the TL flops includes additional multiplexer in front of a standard scan flop and a transition enable (TEN) signal. Moreover, only a heuristically selected subset of scan flip-flops is replaced with the TL flops and only one additional MUX per selected scan flip-flop may contribute an area overhead. Consequently, the overall chip area overhead may be minimal. The present invention may be suitable for being implemented with currently available third party ATPG.

Abstract: Methods for implementing test generation and test application for systematic scan reconfiguration in an integrated circuit. All detectable faults of the integrated circuit are added to a set F. A SAS decoder configuration is selected to start with. ATPG patterns are generated for the faults in the set F for the selected decoder configuration. When F=Ø, a set of patterns Pi is reported for each decoder configuration i?C, where C is a set of selected decoder configurations.