Abstract: A data frame synchronizer identifies frame boundaries in a serial data stream formed of a set of multi-bit frames. Selected frames in the set have a frame boundary bit at a specified location within the frame, and the frame boundary bits together form a predetermined pattern. The frame synchronizer includes a memory array having a memory data input, a memory data output and a plurality of rows and columns for storing the serial data stream. A memory control circuit is coupled to the memory array for writing successive bits of the serial data stream into the memory array through the memory data input in a sequence such that all of the frame boundary bits align in one of the rows. As each bit is being written into the memory array, the memory control circuit reads the corresponding row through the data output. A pattern detector is coupled to the memory data output for comparing the row with a predetermined pattern.