Abstract: A phase interpolator for generating a phase interpolated output signal between two phase separated input signals received at two phase separated input signal nodes may include a plurality of circuit elements. The plurality of circuit elements may include at least one of resistors or capacitors, in a series arrangement between the two phase separated input signal nodes, where respective connection points between respective ones of the plurality of circuit elements may provide at least one intermediate phase interpolated signal. The phase interpolator may also include selection circuitry, which may be configured to select the phase interpolated output signal from the at least one intermediate phase interpolated signal.

Abstract: Described herein are multi-phase clock generator embodiments for compact octal phase generation for high speed clock. A multi-phase clock generator may comprise an in-phase and quadrature (IQ) clock generator that outputs an intermediate clock signal with quad phases and an octal phase generator that generates an output clock signal comprising one or more octal phases and having a clock frequency same as an input 2-phase clock signal to the multi-phase clock generator. The multi-phase clock generator may incorporate a pull-down circuit and a current bias circuit, which may function to improve phase interpolation linearity of the octal phase generator. Histogram of phase shift error comparison shows significant improvement of a multi-phase clock generator embodiment over conventional phase interpolation.

Abstract: Presented are systems and methods for generating quadrature clock signals for high-speed signal processing and similar applications. In various embodiments, a first input signal is rotated by a first phase angle to obtain a first rotated signal that represents a first quadrature clock signal. A second input signal that is 180 degrees out-of-phase with the first signal is rotated by a second phase angle such as to produce a second rotated signal. The unaltered first input signal and the phase-shifted second signal are then combined to derive an interpolated signal. This interpolated signal may be used to generate a second quadrature clock signal. As a result, the presented systems and methods effectively addresses the challenges of low-jitter, high-accuracy clock signal generation in applications such as SERDES and other systems that require precise timing signals, thereby ensuring enhanced system performance, while reducing complexity and power consumption.

Abstract: A low voltage bipolar transconductor circuit with extended dynamic range is disclosed. The transconductance circuit provides a differential current output signal and generally comprises a first and a second differential pair of transistors coupled to a differential input signal and to a load, and having transistors area ratios of 1:r and r:1, respectively. The transconductance circuit further comprises at least one first pair of diodes having positive nodes coupled to each other and to the load, negative nodes coupled to the first differential transistors, and a diode area ratio of r:1, and a least one second pair of diodes having positive nodes coupled to each other and to the load, negative nodes coupled to the second differential transistors, and having a diode area ratio of 1:r.

Abstract: A low power, high performance circuit for magnitude and group delay shaping in continuous-time read channel filters is disclosed. The circuit generally comprises a first and a second biquadratic circuit, each having an input, a band pass, and a output low pass node, where the second biquadratic input node is coupled to the first biquadratic output node, and a first and second transconductor coupled to the first biquadratic band pass node and also to the second biquadratic band pass and low pass output nodes, respectively. The first and second transconductors are preferably programmable transconductors.