Patents by Inventor Narendra Sankar
Narendra Sankar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8666079Abstract: A method includes receiving data which has been encoded according to a first higher complexity protection scheme and compressed. The method also includes decompressing the data. The method also includes decoding the data according to the first higher complexity protection scheme using a first higher complexity key. The method also includes encoding at least the first portion of the data according to a second higher complexity protection scheme using a second higher complexity key. The method also includes encoding at least a second portion of the data according to a lower complexity protection scheme using a lower complexity key.Type: GrantFiled: May 29, 2008Date of Patent: March 4, 2014Assignee: Broadcom CorporationInventors: Chad William Kendall, Narendra Sankar
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Patent number: 8468540Abstract: A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler logic. The logic detects and maps interrupts and exceptions to one or more specific streams. In some embodiments, one interrupt or exception may be mapped to two or more streams, and in others two or more interrupts or exceptions may be mapped to one stream. Mapping may be static and determined at processor design, programmable, with data stored and amendable, or conditional and dynamic, the interrupt logic executing an algorithm sensitive to variables to determine the mapping. Interrupts may be external interrupts generated by devices external to the processor software (internal) interrupts generated by active streams, or conditional, based on variables. After interrupts are acknowledged, streams to which interrupts or exceptions are mapped are vectored to appropriate service routines.Type: GrantFiled: March 7, 2011Date of Patent: June 18, 2013Assignee: Bridge Crossing, LLCInventors: Mario D. Nemirovsky, Adolfo M. Nemirovsky, Narendra Sankar
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Publication number: 20110154347Abstract: A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler logic. The logic detects and maps interrupts and exceptions to one or more specific streams. In some embodiments, one interrupt or exception may be mapped to two or more streams, and in others two or more interrupts or exceptions may be mapped to one stream. Mapping may be static and determined at processor design, programmable, with data stored and amendable, or conditional and dynamic, the interrupt logic executing an algorithm sensitive to variables to determine the mapping. Interrupts may be external interrupts generated by devices external to the processor software (internal) interrupts generated by active streams, or conditional, based on variables. After interrupts are acknowledged, streams to which interrupts or exceptions are mapped are vectored to appropriate service routines.Type: ApplicationFiled: March 7, 2011Publication date: June 23, 2011Inventors: Mario D. NEMIROVSKY, Adolfo M. Nemirovsky, Narendra Sankar
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Patent number: 7926062Abstract: A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler logic. The logic detects and maps interrupts and exceptions to one or more specific streams. In some embodiments, one interrupt or exception may be mapped to two or more streams, and in others two or more interrupts or exceptions may be mapped to one stream. Mapping may be static and determined at processor design, programmable, with data stored and amendable, or conditional and dynamic, the interrupt logic executing an algorithm sensitive to variables to determine the mapping. Interrupts may be external interrupts generated by devices external to the processor software (internal) interrupts generated by active streams, or conditional, based on variables. After interrupts are acknowledged, streams to which interrupts or exceptions are mapped are vectored to appropriate service routines.Type: GrantFiled: April 29, 2009Date of Patent: April 12, 2011Assignee: MIPS Technologies, Inc.Inventors: Mario D. Nemirovsky, Adolfo M. Nemirovsky, Narendra Sankar
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Patent number: 7900207Abstract: A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler logic. The logic detects and maps interrupts and exceptions to one or more specific streams. In some embodiments, one interrupt or exception may be mapped to two or more streams, and in others two or more interrupts or exceptions may be mapped to one stream. Mapping may be static and determined at processor design, programmable, with data stored and amendable, or conditional and dynamic, the interrupt logic executing an algorithm sensitive to variables to determine the mapping. Interrupts may be external interrupts generated by devices external to the processor software (internal) interrupts generated by active streams, or conditional, based on variables. After interrupts are acknowledged, streams to which interrupts or exceptions are mapped are vectored to appropriate service routines.Type: GrantFiled: November 19, 2008Date of Patent: March 1, 2011Assignee: MIPS Technologies, Inc.Inventors: Mario D. Nemirovsky, Adolfo M. Nemirovsky, Narendra Sankar
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Patent number: 7765546Abstract: A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams; and interstream control mechanisms whereby any stream may effect the operation of any other stream. In various embodiments the interstream control mechanisms include mechanisms for accomplishing one or more of enabling or disabling another stream, putting another stream into a sleep mode or awakening another stream from a sleep mode, setting priorities for another stream relative to access to functional resources, and granting blocking access by another stream to functional resources. A Master Mode is taught, wherein one stream is granted master status, and thereby may exert any and all available control mechanisms relative to other streams without interference by any stream.Type: GrantFiled: August 18, 2004Date of Patent: July 27, 2010Assignee: MIPS Technologies, Inc.Inventors: Mario D. Nemirovsky, Adolfo M. Nemirovsky, Narendra Sankar
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Patent number: 7715410Abstract: In a data-packet processor, a configurable queuing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeuing of the selected packet identifiers.Type: GrantFiled: March 23, 2006Date of Patent: May 11, 2010Assignee: MIPS Technologies, Inc.Inventors: Mario Nemirovsky, Enric Musoll, Stephen Melvin, Narendra Sankar, Nandakumar Sampath, Adolfo Nemirovsky
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Patent number: 7661112Abstract: A background event buffer manager (BEBM) for ordering and accounting for events in a data processing system having a processor includes a port for receiving event identifications (IDs) from a device, a queuing function enabled for queuing event IDs received, and a notification function for notifying the processor of queued event IDs. The BEBM handles all event ordering and accounting for the processor. The BEBM in preferred embodiments queues events by type with priority and by priority within type, and also handles sending acknowledgement to the device when processing on each event is concluded, and buffers the acknowledgement process. In particular embodiments the apparatus and method is taught as a packet processing router engine.Type: GrantFiled: April 5, 2006Date of Patent: February 9, 2010Assignee: MIPS Technologies, Inc.Inventors: Mario Nemirovsky, Narendra Sankar, Adolfo Nemirovsky, Enric Musoll
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Patent number: 7636836Abstract: A dynamic multistreaming processor has instruction queues, each instruction queue corresponding to an instruction stream, and execution units. The dynamic multistreaming processor also has a dispatch stage to select at least one instruction from one of the instruction queues and to dispatch the selected at least one instruction to one of the execution units. Lastly the dynamic multistreaming processor has a queue counter, associated with each instruction queue, for indicating the number of instructions in each queue, and a fetch counter, associated with each instruction queue, for indicating an address from which to obtain instructions when the associated instruction queue is not full. The dynamic multistreaming processor might also have fetch counters for indicating a next instruction address from which to obtain at least one instruction when the associated instruction queue is not full. The dynamic multistreaming processor could also have a second counter for indicating a next instruction address.Type: GrantFiled: July 15, 2008Date of Patent: December 22, 2009Assignee: MIPS Technologies, Inc.Inventors: Mario D. Nemirovsky, Adolfo M. Nemirovsky, Narendra Sankar, Enrique Musoll
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Publication number: 20090296935Abstract: Various example embodiments are disclosed. According to an example embodiment, a method may include receiving data which has been encoded according to a first higher complexity protection scheme and compressed. The method may also include decompressing the data. The method may also include decoding the data according to the first higher complexity protection scheme using a first higher complexity key. The method may also include encoding at least the first portion of the data according to a second higher complexity protection scheme using a second higher complexity key. The method may also include encoding at least a second portion of the data according to a lower complexity protection scheme using a lower complexity key.Type: ApplicationFiled: May 29, 2008Publication date: December 3, 2009Applicant: Broadcom CorporationInventors: Chad William Kendall, Narendra Sankar
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Publication number: 20090241119Abstract: A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler logic. The logic detects and maps interrupts and exceptions to one or more specific streams. In some embodiments, one interrupt or exception may be mapped to two or more streams, and in others two or more interrupts or exceptions may be mapped to one stream. Mapping may be static and determined at processor design, programmable, with data stored and amendable, or conditional and dynamic, the interrupt logic executing an algorithm sensitive to variables to determine the mapping. Interrupts may be external interrupts generated by devices external to the processor software (internal) interrupts generated by active streams, or conditional, based on variables. After interrupts are acknowledged, streams to which interrupts or exceptions are mapped are vectored to appropriate service routines.Type: ApplicationFiled: April 29, 2009Publication date: September 24, 2009Inventors: Mario D. Nemirovsky, Adolfo M. Nemirovsky, Narendra Sankar
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Publication number: 20090187739Abstract: Load and store operations in computer systems are extended to provide for Stream Load and Store and Masked Load and Store. In Stream operations, a CPU executes a Stream instruction that indicates, by appropriate arguments, a first address in memory or a first register in a register file from whence to begin reading data entities, and a first address or register from whence to begin storing the entities, and a number of entities to be read and written. In Masked Load and Masked Store operations stored masks are used to indicate patterns relative to first addresses and registers for loading and storing. Bit-string vector methods are taught for masks.Type: ApplicationFiled: March 26, 2009Publication date: July 23, 2009Inventors: Mario NEMIROVSKY, Enrique Musoll, Narendra Sankar, Stephen Melvin
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Patent number: 7551626Abstract: In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeueing of the selected packet identifiers.Type: GrantFiled: February 23, 2006Date of Patent: June 23, 2009Assignee: MIPS Technologies, Inc.Inventors: Mario Nemirovsky, Enric Musoll, Stephen Melvin, Narendra Sankar, Nandakumar Sampath, Adolfo Nemirovsky
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Publication number: 20090125660Abstract: A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler logic. The logic detects and maps interrupts and exceptions to one or more specific streams. In some embodiments, one interrupt or exception may be mapped to two or more streams, and in others two or more interrupts or exceptions may be mapped to one stream. Mapping may be static and determined at processor design, programmable, with data stored and amendable, or conditional and dynamic, the interrupt logic executing an algorithm sensitive to variables to determine the mapping. Interrupts may be external interrupts generated by devices external to the processor software (internal) interrupts generated by active streams, or conditional, based on variables. After interrupts are acknowledged, streams to which interrupts or exceptions are mapped are vectored to appropriate service routines.Type: ApplicationFiled: November 19, 2008Publication date: May 14, 2009Applicant: MIPS Technologies, Inc.Inventors: Mario D. Nemirovsky, Adolfo M. Nemirovsky, Narendra Sankar
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Patent number: 7529907Abstract: Load and store operations in computer systems are extended to provide for Stream Load and Store and Masked Load and Store. In Stream operations a CPU executes a Stream instruction that indicates by appropriate arguments a first address in memory or a first register in a register file from whence to begin reading data entities, and a first address or register from whence to begin storing the entities, and a number of entities to be read and written. In Masked Load and Masked Store operations stored masks are used to indicate patterns relative to first addresses and registers for loading and storing. Bit-string vector methods are taught for masks.Type: GrantFiled: October 22, 2007Date of Patent: May 5, 2009Assignee: MIPS Technologies, Inc.Inventors: Mario D. Nemirovsky, Stephen Melvin, Enrique Musoll, Narendra Sankar
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Publication number: 20090110051Abstract: The disclosed systems and methods relate to reducing the effect of video processing latency in devices that utilize PCI Express Active State Power Management (PCI-E ASPM). Power state transition delay may be reduced by initiating an early L1 exit based on a video processing stimulus. Aspects of the present invention may enable a higher level of performance and responsiveness while supporting the benefits of ASPM. Aspects of the present invention may be embodied in a video processing device that uses a video accelerator with a PCI-E interface.Type: ApplicationFiled: October 29, 2007Publication date: April 30, 2009Inventors: Steven B. Lindsay, Narendra Sankar, Chad Kendall
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Patent number: 7502876Abstract: A background memory manager (BMM) for managing a memory in a data processing system has circuitry for transferring data to and from an outside device and to and from a memory, a memory state map associated with the memory, and a communication link to a processor. The BMM manages the memory, determining if each data structure fits into the memory, deciding exactly where to place the data structure in memory, performing all data transfers between the outside device and the memory, and maintaining the memory state map according to memory transactions made, and informing the processor of new data and its location. In preferred embodiments the BMM, in the process of storing data structures into the memory, provides an identifier for each structure to the processor. The system is particularly applicable to Internet packet processing in packet routers.Type: GrantFiled: June 23, 2000Date of Patent: March 10, 2009Assignee: MIPS Technologies, Inc.Inventors: Mario Nemirovsky, Narendra Sankar, Adolfo Nemirovsky, Enric Musoll
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Patent number: 7467385Abstract: A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler logic. The logic detects and maps interrupts and exceptions to one or more specific streams. In some embodiments one interrupt or exception may be mapped to two or more streams, and in others two or more interrupts or exceptions may be mapped to one stream. Mapping may be static and determined at processor design, programmable, with data stored and amendable, or conditional and dynamic, the interrupt logic executing an algorithm sensitive to variables to determine the mapping. Interrupts may be external interrupts generated by devices external to the processor software (internal) interrupts generated by active streams, or conditional, based on variables. After interrupts are acknowledged streams to which interrupts or exceptions are mapped are vectored to appropriate service routines.Type: GrantFiled: March 21, 2006Date of Patent: December 16, 2008Assignee: MIPS Technologies, Inc.Inventors: Adolfo M Nemirovsky, Mario D Nemirovsky, Narendra Sankar
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Publication number: 20080270757Abstract: A dynamic multistreaming processor has instruction queues, each instruction queue corresponding to an instruction stream, and execution units. The dynamic multistreaming processor also has a dispatch stage to select at least one instruction from one of the instruction queues and to dispatch the selected at least one instruction to one of the execution units. Lastly the dynamic multistreaming processor has a queue counter, associated with each instruction queue, for indicating the number of instructions in each queue, and a fetch counter, associated with each instruction queue, for indicating an address from which to obtain instructions when the associated instruction queue is not full. The dynamic multistreaming processor might also have fetch counters for indicating a next instruction address from which to obtain at least one instruction when the associated instruction queue is not full. The dynamic multistreaming processor could also have a second counter for indicating a next instruction address.Type: ApplicationFiled: July 15, 2008Publication date: October 30, 2008Applicant: MIPS Technologies, Inc.Inventors: Mario Nemirovsky, Adolfo Nemirovsky, Narendra Sankar, Enrique Musoll
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Patent number: 7406586Abstract: A pipelined multistreaming processor has an instruction source, a plurality of streams fetching instructions from the instruction source, a dispatch stage for selecting and dispatching instructions to a set of execution units, a set of instruction queues having one queue associated with each stream in the plurality of streams, and located in the pipeline between the instruction cache and the dispatch stage, and a select system for selecting streams in each cycle to fetch instructions from the instruction cache. The processor is characterized in that the select system selects one or more streams in each cycle for which to fetch instructions from the instruction cache, and in that the number of streams selected for which to fetch instructions in each cycle is fewer than the number of streams in the plurality of streams.Type: GrantFiled: October 6, 2006Date of Patent: July 29, 2008Assignee: MIPS Technologies, Inc.Inventors: Mario Nemirovsky, Adolfo Nemirovsky, Narendra Sankar, Enrique Musoll