Patents by Inventor Naresh BATTULA

Naresh BATTULA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10915133
    Abstract: A voltage regulator circuit is presented that can generate a stable and well-regulated output level to supply loads that have large dynamic current and capacitive variation. A compensation circuit is added to introduce a zero that tracks the voltage regulator's non-dominant pole. The compensation circuit includes a compensation transistor, whose gate is connected to receive the same voltage as the regulator's load driving pass transistor, and a series combination of a capacitance and a tracking resistance connected in series between the compensation transistor's gate and a supply level, where the value of the tracking resistance depends on the current supplied to the load. The tracking resistance can be implemented as a diode connected NMOS through which the compensation transistor is connected to the low supply level, or a diode connected PMOS whose current tracks that of the compensation transistor through a current mirror.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: February 9, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Xiaofeng Zhang, Naresh Battula, Albert I-Ming Chang
  • Patent number: 10908210
    Abstract: Systems and methods for die crack detection are disclosed. In one exemplary embodiment, a die includes a first conductive segment, an intermediate conductive segment, and a second conductive segment. The crack detection ring substantially surrounds the die according to a serpentine path having a plurality of legs, wherein each leg intersects the first conductive segment at a first intersection, an intermediate conductive segment at an intermediate intersection and a second conductive segment at a second intersection, wherein the intermediate intersection is horizontally offset from at least the first intersection and the second intersection.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: February 2, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Kirubakaran Periyannan, Naresh Battula, Chang Siau
  • Publication number: 20200103462
    Abstract: Systems and methods for die crack detection are disclosed. In one exemplary embodiment, a die includes a first conductive segment, an intermediate conductive segment, and a second conductive segment. The crack detection ring substantially surrounds the die according to a serpentine path having a plurality of legs, wherein each leg intersects the first conductive segment at a first intersection, an intermediate conductive segment at an intermediate intersection and a second conductive segment at a second intersection, wherein the intermediate intersection is horizontally offset from at least the first intersection and the second intersection.
    Type: Application
    Filed: April 30, 2019
    Publication date: April 2, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Kirubakaran PERIYANNAN, Naresh BATTULA, Chang SIAU