Abstract: A data processing system having a distributed reservation station is provided which stores basic blocks of code in the form of microprocessor instructions. The present invention is capable of distributing basic blocks of code to the various distributed reservation stations. Due to the smaller number of entries in the distributed reservation stations, the look up time required to find a particular instruction is much less than in a centralized reservation station. Additional instruction level parallelism is achieved by maintaining single basic blocks of code in the distributed reservation stations. With a distributed reservation station, an independent scheduler can be used for each one of the distributed reservation stations. When the instruction is ready for execution, the scheduler will remove that instruction from the distributed reservation station and queue that instruction(s) for immediate execution at the particular execution unit.

Abstract: The present invention utilizes a “virtual” condition code (VCC) which can control the instruction sequence in a microprocessor. The virtual condition code is stored in an internal, non-architected register that is not visible to the programmer, but is used by various microprocessor instructions to determine when a branch is to be taken. For example, the virtual condition code can be used as a condition for branching out of a series of repetitive instructions. The virtual condition code (VCC) can eliminate a portion of the processing overhead used when determining whether a sequential number, such as a count value in a register associated with a repetitive instruction, e.g. a LOOP, is zero. In accordance with one aspect of the present invention, a LOOP instruction will decrement a count value in a register (to maintain compatibility with the ISA).

Abstract: A system and method is provided to reduce the latency associated with saving and restoring the state of the floating point registers in a microprocessor when switching tasks between floating point and MMX operations, or between tasks within the same context. The present invention maintains a secondary register file along with the primary floating point register file in the CPU. The primary register will keep the state of the floating point task “as is” upon the occurrence of a task switch to MMX, or another context. The address of the area where the FPU state is saved is maintained in a save area address register. The secondary register is then utilized by the other context to store intermediate results of executed instructions. In the majority of cases when a context switch back to floating point operations occurs, the previous state is restored from the primary register without incurring the latency of retrieving the instructions and data from the memory subsystem.

Abstract: A data processing system having a distributed reservation station is provided which stores basic blocks of code in the form of microprocessor instructions. The present invention is capable of distributing basic blocks of code to the various distributed reservation stations. Due to the smaller number of entries in the distributed reservation stations, the look up time required to find a particular instruction is much less than in a centralized reservation station. Additional instruction level parallelism is achieved by maintaining single basic blocks of code in the distributed reservation stations. This is because instructions which are grouped together are less likely to use the same resources, e.g. registers and memory locations, therefore, they will exhibit more data, control and resource independence. In contrast, when instructions are not associated with one another (e.g.

Abstract: The present invention utilizes a “virtual” condition code (VCC) which can control the instruction sequence in a microprocessor. The virtual condition code is stored in an internal, non-architected register that is not visible to the programmer, but is used by various microprocessor instructions to determine when a branch is to be taken. For example, the virtual condition code can be used as a condition for branching out of a series of repetitive instructions. The virtual condition code (VCC) can eliminate a portion of the processing overhead used when determining whether a sequential number, such as a count value in a register associated with a repetitive instruction, e.g. a LOOP, is zero. In accordance with one aspect of the present invention, a LOOP instruction will decrement a count value in a register (to maintain compatibility with the ISA).