Patents by Inventor Naresh Kumar Sharma

Naresh Kumar Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11556346
    Abstract: Methods and systems for allowing software components that operate at a specific exception level (e.g., EL-3 to EL-1, etc.) to repeatedly or continuously observe or evaluate the integrity of software components operating at a lower exception level (e.g., EL-2 to EL-0) to ensure that the software components have not been corrupted or compromised (e.g., subjected to malware, cyberattacks, etc.) include a computing device that identifies, by a component operating at a higher exception level (“HEL component”), at least one of a current vector base address (VBA), an exception raising instruction (ERI) address, or a control and system register value associated with a component operating at a lower exception level (“LEL component”). The computing device may perform a responsive action in response to determining that the current VBA, the ERT address, or control and system register value do not match the corresponding reference data.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: January 17, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Naresh Kumar Sharma, Saurabh Gorecha, Pravin Kumar
  • Patent number: 11204781
    Abstract: A method of loading an executable image for a computing system includes identifying segments of at least one executable image available for loading into memory of the computing system. Each segment is associated with one or more configuration features for the computing system. At least a first segment of the at least one executable image to load into the memory of the computing system is determined, based on the first segment satisfying one or more conditions associated with the computing system. The first segment of the executable image is loaded into the memory of the computing system. At least a second segment of the at least one executable image is made available for memory re-allocation, based on the second segment not satisfying the one or more conditions associated with the computing system. Various additional and alternative aspects are described herein.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: December 21, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Saurabh Gorecha, Naresh Kumar Sharma, Pravin Kumar
  • Publication number: 20210389953
    Abstract: Methods and systems for allowing software components that operate at a specific exception level (e.g., EL-3 to EL-1, etc.) to repeatedly or continuously observe or evaluate the integrity of software components operating at a lower exception level (e.g., EL-2 to EL-0) to ensure that the software components have not been corrupted or compromised (e.g., subjected to malware, cyberattacks, etc.) include a computing device that identifies, by a component operating at a higher exception level (“HEL component”), at least one of a current vector base address (VBA), an exception raising instruction (ERI) address, or a control and system register value associated with a component operating at a lower exception level (“LEL component”). The computing device may perform a responsive action in response to determining that the current VBA, the ERT address, or control and system register value do not match the corresponding reference data.
    Type: Application
    Filed: June 10, 2020
    Publication date: December 16, 2021
    Inventors: Naresh Kumar SHARMA, Saurabh GORECHA, Pravin KUMAR
  • Patent number: 11113074
    Abstract: Various embodiments of methods and systems for a modem-directed application processor boot flow in a portable computing device (“PCD”) are disclosed. An exemplary method includes an application processor that transitions into an idle state, such as a WFI state, for durations of time during a boot sequence that coincide with processing by a DMA engine and/or crypto engine. That is, the application processor may “sleep” while the DMA engine and/or crypto engine process workloads in response to instructions they received from the application processor.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: September 7, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Saurabh Gorecha, Naresh Kumar Sharma, Pravin Kumar, Dexter Tamio Chun, Christopher Kong Yee Chun
  • Publication number: 20210182081
    Abstract: A method of loading an executable image for a computing system includes identifying segments of at least one executable image available for loading into memory of the computing system. Each segment is associated with one or more configuration features for the computing system. At least a first segment of the at least one executable image to load into the memory of the computing system is determined, based on the first segment satisfying one or more conditions associated with the computing system. The first segment of the executable image is loaded into the memory of the computing system. At least a second segment of the at least one executable image is made available for memory re-allocation, based on the second segment not satisfying the one or more conditions associated with the computing system. Various additional and alternative aspects are described herein.
    Type: Application
    Filed: December 11, 2019
    Publication date: June 17, 2021
    Inventors: Saurabh GORECHA, Naresh Kumar SHARMA, Pravin KUMAR
  • Publication number: 20210064383
    Abstract: Aspects of the disclosure relate to improving device boot up time and subsystem availability time in a computing system using segment read scheduling. The segment read scheduling is a scheduling of order for loading subsystem images for a number of subsystem images from a memory during boot up or reset of the computing system and is based on a determined criticality value calculated from various parameters including subsystem image size, the priority of the subsystem. Additionally, the scheduled segment loading is performed according to numerous parallel loading schemes using multiple direct memory access engines and cryptography engines to increase the speed of loading the images and bringing them out of boot up or reset. Other aspects, embodiments, and features are also claimed and described.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 4, 2021
    Inventors: Naresh Kumar SHARMA, Pravin KUMAR, Saurabh GORECHA
  • Publication number: 20200409721
    Abstract: Various embodiments of methods and systems for a modem-directed application processor boot flow in a portable computing device (“PCD”) are disclosed. An exemplary method includes an application processor that transitions into an idle state, such as a WFI state, for durations of time during a boot sequence that coincide with processing by a DMA engine and/or crypto engine. That is, the application processor may “sleep” while the DMA engine and/or crypto engine process workloads in response to instructions they received from the application processor.
    Type: Application
    Filed: November 19, 2019
    Publication date: December 31, 2020
    Inventors: SAURABH GORECHA, NARESH KUMAR SHARMA, PRAVIN KUMAR, DEXTER TAMIO CHUN, CHRISTOPHER KONG YEE CHUN
  • Patent number: 7366098
    Abstract: A method is described that resets a first count and resets a second count if a first transmission unit is recognized as being within a new measurement time window. The first transmission unit has a size. The method also increments the first count by the first transmission unit size and by the size of each subsequent transmission unit that is received within the new measurement time window after the first transmission unit—so long as the first count does not exceed a maximum allowable value for the first count. The method also checks if a maximum value for the second count is exceeded if it is incremented by a second transmission unit size. The second transmission unit is received within the measurement time window. The check is in response to a determination that the first count would have exceeded the first count maximum allowable valuable if the first count were incremented by the second transmission unit size.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: April 29, 2008
    Assignee: Cisco Technology, Inc.
    Inventors: Raja Rangarjan, Ashish Gupta, Rohit Sharma, Naresh Kumar Sharma, Frederic Mathieu, Jayakumar Jayakumar