Patents by Inventor Naresh Nayer

Naresh Nayer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9092297
    Abstract: A firmware update process for a self-virtualizing IO resource such as an SRIOV adapter is incorporated into a platform firmware update process to systematically update the resource firmware in a manner that is for the most part transparent to the logical partitions sharing the adapter. In particular, resource firmware associated with a self-virtualizing IO resource is bundled with firmware for at least one adjunct partition associated with that self-virtualizing IO resource within a common firmware image so that, upon restart of the adjunct partition to use the updated firmware image, the resource firmware is also updated, with a logical partition that uses the self-virtualizing IO resource maintained in an active state during the restart, and without requiring the self-virtualizing IO resource to be deconfigured from the logical partition.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: July 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: William J. Armstrong, Charles S. Graham, Andrew T. Koch, Kyle A. Lucke, Naresh Nayer, Randal C. Swanberg
  • Patent number: 8108196
    Abstract: An apparatus and program product for coordinating the distribution of CPUs as among logically-partitioned virtual processors. A virtual processor may yield a CPU to precipitate an occurrence upon which its own execution may be predicated. As such, program code may dispatch the surrendered CPU to a designated virtual processor.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: January 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: William Joseph Armstrong, Chris Francois, Naresh Nayer
  • Patent number: 7478268
    Abstract: A method, apparatus, system, and computer-readable storage medium that, in an embodiment, set uncorrectable error indicators in logical memory blocks in response to detecting an uncorrectable error in memory pages associated with the logical memory blocks. If the logical memory block is allocated to a hypervisor, the memory page may be deallocated in response to detection of the uncorrectable error. When an IPL of a partition is subsequently performed, a determination is made whether a logical memory block allocated to the partition previously encountered the uncorrectable error via the uncorrectable error indicator. If the logical memory block did previously encounter the uncorrectable error, the logical memory block is deallocated from the partition. In an embodiment, if spare memory exists, the logical memory block with the previously encountered uncorrectable error is replaced with the spare memory and the IPL of the partition is continued with the spare memory.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: January 13, 2009
    Assignee: International Business Machines Corporation
    Inventors: Daniel James Henderson, Alongkorn Kitamorn, Wayne Lemmon, Naresh Nayer, Wade Byron Ouren