Patents by Inventor Naresh Shanbhag
Naresh Shanbhag has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9697877Abstract: A compute memory system can include a memory array and a controller that generates N-ary weighted (e.g., binary weighted) access pulses for a set of word lines during a single read operation. This multi-row read generates a charge on a bit line representing a word stored in a column of the memory array. The compute memory system further includes an embedded analog signal processor stage through which voltages from bit lines can be processed in the analog domain. Data is written into the memory array in a manner that stores words in columns instead of the traditional row configuration.Type: GrantFiled: February 5, 2015Date of Patent: July 4, 2017Assignee: THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOISInventors: Naresh Shanbhag, Mingu Kang, Min-Sun Keel
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Publication number: 20160232951Abstract: A compute memory system can include a memory array and a controller that generates N-ary weighted (e.g., binary weighted) access pulses for a set of word lines during a single read operation. This multi-row read generates a charge on a bit line representing a word stored in a column of the memory array. The compute memory system further includes an embedded analog signal processor stage through which voltages from bit lines can be processed in the analog domain. Data is written into the memory array in a manner that stores words in columns instead of the traditional row configuration.Type: ApplicationFiled: February 5, 2015Publication date: August 11, 2016Inventors: NARESH SHANBHAG, MINGU KANG, MIN-SUN KEEL
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Patent number: 8462037Abstract: An adaptive Analog to Digital Converter (ADC) that adjusts the representation levels used in the conversion process so as to optimize system performance. By establishing system performance criteria by which to select or adjust the signal value range associated with each digital representation and/or the digital representation, substantially fewer bits may be used in the ADC. The systems and methods described herein enable lower-power, smaller form-factor designs as well as very high-speed operation. In particular, this technology may be beneficial for use in communications systems because it enables ADC's to operate at speeds where traditional ADC designs simply cannot.Type: GrantFiled: November 15, 2010Date of Patent: June 11, 2013Assignee: The Board of Trustees of the University of IllinoisInventors: Andrew Carl Singer, Naresh Shanbhag
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Publication number: 20110115660Abstract: An adaptive Analog to Digital Converter (ADC) that adjusts the representation levels used in the conversion process so as to optimize system performance. By establishing system performance criteria by which to select or adjust the signal value range associated with each digital representation and/or the digital representation, substantially fewer bits may be used in the ADC. The systems and methods described herein enable lower-power, smaller form-factor designs as well as very high-speed operation. In particular, this technology may be beneficial for use in communications systems because it enables ADC's to operate at speeds where traditional ADC designs simply cannot.Type: ApplicationFiled: November 15, 2010Publication date: May 19, 2011Applicants: of IllinoisInventors: Andrew Carl Singer, Naresh Shanbhag
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Patent number: 7834692Abstract: A peak detector circuit that responds rapidly to power transients, and yet is able to avoid interpreting data fluctuations as power transients by generating dual peak signals from an amplifier's differential output signal, where the dual peak signals have data ripple components that tend to cancel one another. The system and methods permit the peak detectors to be much more responsive to power transients by expanding their bandwidth (shortening the time constants) to the point that low frequency data components affect the individual peak detector signals, but the effects are cancelled out when the individual components are added together. The peak detector described herein may be used in an AGC system to provide ripple-free gain control signals, while rapidly following any power transients in transmitted signals.Type: GrantFiled: September 17, 2007Date of Patent: November 16, 2010Assignee: Finisar CorporationInventors: Hyeon Min Bae, Naresh Shanbhag, Jonathan B. Ashbrook
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Patent number: 7609102Abstract: A phase detector apparatus and method used for clock recovery from a data signal is provided. The phase detector provides phase correction signals to a clock signal generator, where the phase correction signals are only generated if a predetermined data sample pattern is observed. In particular, the predetermined data sample pattern is preferably a transition from one to zero. Thus, transitions from zero to one will not provide a valid phase update output signal, even though a transition has occurred. In other embodiments the predetermined data sample pattern is preferably a one to zero transition preceded by an additional logic one sample.Type: GrantFiled: May 24, 2006Date of Patent: October 27, 2009Assignee: Finisar CorporationInventors: Naresh Shanbhag, Hyeon Min Bae, Jinki Park, Paul Suppiah
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Publication number: 20090237138Abstract: A phase detector apparatus and method used for clock recovery from a data signal is provided. The phase detector provides phase correction signals to a clock signal generator, where the phase correction signals are only generated if a predetermined data sample pattern is observed. In particular, the predetermined data sample pattern is preferably a transition from one to zero. Thus, transitions from zero to one will not provide a valid phase update output signal, even though a transition has occurred. In other embodiments the predetermined data sample pattern is preferably a one to zero transition preceded by an additional logic one sample.Type: ApplicationFiled: May 24, 2006Publication date: September 24, 2009Applicant: INTERSYMBOL COMMUNICATIONS, INC.Inventors: Naresh Shanbhag, Hyeon Min Bae, Jinki Park, Paul Suppiah
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Patent number: 7298226Abstract: A noise tolerant voltage controlled oscillator is described. The voltage controlled oscillator include a varactor element as part of an LC tank circuit. The varactor element is biased by a bias signal and a bias-dependent control signal. The bias-dependent control signal tunes the LC tank circuit. Because the control signal is bias-dependent, noise and other deleterious influences do not cause the varactor element to deviate in capacitance. Instead, the bias-dependent control signal is a tuning signal that is centered around the bias signal, which allows the varactor element to provide a constant capacitance in the event of a varying bias signal.Type: GrantFiled: May 24, 2006Date of Patent: November 20, 2007Assignee: Finisar CorporationInventors: Naresh Shanbhag, Hyeon Min Bae, Jinki Park, Paul Suppiah
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Publication number: 20070226572Abstract: A method for improving reliability of an electronic system by evaluating a soft error rate is disclosed. A gate-level representation of the electronic system is converted to a graph, the graph having vertices and edges that correspond to nodes and gates of the electronic system. Input vectors are generated, which correspond to inputs supplied to the electronic system. A soft error rate for the electronic system is evaluated during a simulated operation of the electronic system, and the evaluated soft error rate is correlated to a set of parameters used to configure the electronic system.Type: ApplicationFiled: November 2, 2006Publication date: September 27, 2007Inventors: Ming Zhang, Naresh Shanbhag
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Publication number: 20070018742Abstract: A noise tolerant voltage controlled oscillator is described. The voltage controlled oscillator include a varactor element as part of an LC tank circuit. The varactor element is biased by a bias signal and a bias-dependent control signal. The bias-dependent control signal tunes the LC tank circuit. Because the control signal is bias-dependent, noise and other deleterious influences do not cause the varactor element to deviate in capacitance. Instead, the bias-dependent control signal is a tuning signal that is centered around the bias signal, which allows the varactor element to provide a constant capacitance in the event of a varying bias signal.Type: ApplicationFiled: May 24, 2006Publication date: January 25, 2007Applicant: INTERSYMBOL COMMUNICATIONS, INC.Inventors: Naresh Shanbhag, Hyeon Bae, Jinki Park, Paul Suppiah