Abstract: An accumulation mode FET (ACCUFET) which includes an insulated gate, an adjacently disposed insulated source field electrode, and a source contact that makes Schottky contact with the base region of the ACCUFET.

Abstract: A process for manufacturing a semiconductor device of the trench variety with reduced feature sizes and improved characteristics which process includes forming a termination structure having a field oxide disposed in a recess below the surface of the semiconductor die in which the active elements of the device are formed, and forming source regions after the major thermal steps have been performed.

Abstract: A MOSgated device has spaced vertical trenches lined with a gate oxide and filled with a P type polysilicon gate. The gate oxide extends along a vertical N? channel region disposed between an N+ source region and an N? drift region. A Schottky barrier of aluminum is disposed adjacent the accumulation region extending along the trench to collect holes which are otherwise injected into the source region during voltage blocking. A common source or drain contact is connected to the N+ region and to the Schottky contact. A two gate embodiment is disclosed in which separately energized gates are connected to alternatively located gate polysilicon volumes.

Abstract: A trench type power MOSFET has a thin vertical gate oxide along its side walls and a thickened oxide with a rounded bottom at the bottom of the trench to provide a low RDSON and increased VDSMAX and VGSMAX and a reduced Miller capacitance. The walls of the trench are first lined with nitride to permit the growth of the thick bottom oxide to, for example 1000 ? to 1400 ? and the nitride is subsequently removed and a thin oxide, for example 320 ? is regrown on the side walls. In another embodiment, the trench bottom in amorphized and the trench walls are left as single crystal silicon so that oxide can be grown much faster and thicker on the trench bottom than on the trench walls during an oxide growth step. A reduced channel length of about 0.7 microns is used. The source diffusion is made deeper than the implant damage depth so that the full 0.7 micron channel is along undamaged silicon.

Abstract: A trench power semiconductor device including a recessed termination structure.

Abstract: A trench type power MOSFET has a thin vertical gate oxide along its side walls and a thickened oxide with a rounded bottom at the bottom of the trench to provide a low RDSON and increased VDSMAX and VGSMAX and a reduced Miller capacitance. The walls of the trench are first lined with nitride to permit the growth of the thick bottom oxide to, for example 1000 Å to 1400 Å and the nitride is subsequently removed and a thin oxide, for example 320 Å is regrown on the side walls. In another embodiment, the trench bottom in amorphized and the trench walls are left as single crystal silicon so that oxide can be grown much faster and thicker on the trench bottom than on the trench walls during an oxide growth step. A reduced channel length of about 0.7 microns is used. The source diffusion is made deeper than the implant damage depth so that the full 0.7 micron channel is along undamaged silicon.

Abstract: A process for manufacturing a semiconductor device of the trench variety with reduced feature sizes and improved characteristics which process includes forming a termination structure having a field oxide disposed in a recess below the surface of the semiconductor die in which the active elements of the device are formed, and forming source regions after the major thermal steps have been performed.

Abstract: A MOSgated device has spaced vertical trenches lined with a gate oxide and filled with a P type polysilicon gate. The gate oxide extends along a vertical N− channel region disposed between an N+ source region and an N− drift region. A Schottky barrier of aluminum is disposed adjacent the accumulation region extending along the trench to collect holes which are otherwise injected into the source region during voltage blocking. A common source or drain contact is connected to the N+ region and to the Schottky contact. A two gate embodiment is disclosed in which separately energized gates are connected to alternatively located gate polysilicon volumes.

Abstract: A trench type power MOSFET has a thin vertical gate oxide along its side walls and a thickened oxide with a rounded bottom at the bottom of the trench to provide a low RDSON and increased VDSMAX and VGSMAX and a reduced Miller capacitance. The walls of the trench are first lined with nitride to permit the growth of the thick bottom oxide to, for example 1000 Å to 1400 Å and the nitride is subsequently removed and a thin oxide, for example 320 Å is regrown on the side walls. In another embodiment, the trench bottom in amorphized and the trench walls are left as single crystal silicon so that oxide can be grown much faster and thicker on the trench bottom than on the trench walls during an oxide growth step. A reduced channel length of about 0.7 microns is used. The source diffusion is made deeper than the implant damage depth so that the full 0.7 micron channel is along undamaged silicon.

Abstract: A trench type power MOSFET has a thin vertical gate oxide along its side walls and a thickened oxide with a rounded bottom at the bottom of the trench to provide a low RDSON and increased VDSMAX and VGSMAX and a reduced Miller capacitance. The walls of the trench are first lined with nitride to permit the growth of the thick bottom oxide to, for example 1000 Å to 1400 Å and the nitride is subsequently removed and a thin oxide, for example 320 Å is regrown on the side walls. In another embodiment, the trench bottom in amorphized and the trench walls are left as single crystal silicon so that oxide can be grown much faster and thicker on the trench bottom than on the trench walls during an oxide growth step. A reduced channel length of about 0.7 microns is used. The source diffusion is made deeper than the implant damage depth so that the full 0.7 micron channel is along undamaged silicon.

Abstract: A trench type power MOSgated device has a plurality of spaced trenches lined with oxide and filled with conductive polysilicon. The tops of the polysilicon fillers are below the top silicon surface and are capped with a deposited oxide the top of which is flush with the top of the silicon. Source regions of short lateral extent extend into the trench walls to a depth below the top of the polysilicon. A trench termination is formed having an insulation oxide liner covered by a polysilicon layer, covered in turn by a deposited oxide.

Abstract: An SO-8 type package contains a control MOSFET die mounted on one lead frame section and a synchronous MOSFET and Schottky diode die is mounted on a second lead frame pad section. The die are interconnected through the lead frame pads and wire bonds to define a buck converter circuit and the die and lead frame pads are overmolded with a common insulation housing.

Abstract: A MOSgated device with a minimum overlap between the gate and drain electrodes is comprised of an N+ substrate which receives an epitaxial layer of silicon. The body of the epitaxial layer has an N− lower layer for an accumulation device or a P− drift lower layer. In each case the top of the epitaxial layer is N+. Both can be operated in an a-c mode. A trench gate consists of a trench through the epitaxial layer which has a thin gate oxide layer on its walls and bottom and a conductive polysilicon gate body filling the trench. The thin oxide on the bottom of the trench may be thicker than the oxide on the walls to reduce gate capacitance. A thick isolation oxide which is about 10 times as thick as the gate oxide overlies the top of the polysilicon. A planar drain electrode overlies the N+ top layer and the laterally spaced isolation oxide; and a planar source electrode contacts the bottom of the substrate.

Abstract: A semiconductor device includes: at least first, second, and third semiconductor dice, each having opposing surfaces which contain respective electrodes; a conductive lead frame including first and second separate die pad areas, the first and second semiconductor dice being disposed on the first die pad, and the third semiconductor die being disposed on the second die pad; a first plurality of pins being integral with and extending from one edge of the first die pad; a second plurality of pins being integral with and extending from one edge of the second die pad; a third plurality of pins being separated from one another and from the first and second die pads; a first plurality of bonding wires connecting one surface of the first semiconductor die to at least one of the third plurality of pins; a second plurality of bonding wires connecting one surface of the third semiconductor die to at least another one of the third plurality of pins; and a housing for encapsulating the lead frame, semiconductor dice, and

Abstract: A MOSgated device with a minimum overlap between the gate and drain electrodes is comprised of an N+ substrate which receives an epitaxial layer of silicon. The body of the epitaxial layer has an N- lower layer for an accumulation device or a P− drift lower layer. In each case the top of the epitixial layer is N+. Both can be operated in an a-c mode. A trench gate consists of a trench through the epitaxial layer which has a thin gate oxide layer on its walls and bottom and a conductive polysilicon gate body filling the trench. The thin oxide on the bottom of the trench may be thicker than the oxide on the walls to reduce gate capacitance. A thick isolation oxide which is about 10 times as thick as the gate oxide overlies the top of the polysilicon. A planar drain electrode overlies the N+ top layer and the laterally spaced isolation oxide; and a planar source electrode contacts the bottom of the substrate.

Abstract: An SO-8 type package contains a control MOSFET die mounted on one lead frame section and a synchronous MOSFET and Schottky diode die is mounted on a second lead frame pad section. The die are interconnected through the lead frame pads and wire bonds to define a buck converter circuit and the die and lead frame pads are overmolded with a common insulation housing.

Abstract: A trench type power MOSFET has a thin vertical gate oxide along its side walls and a thickened oxide with a rounded bottom at the bottom of the trench to provide a low RDSON and increased VDSMAX and VGSMAX and a reduced Miller capacitance. The walls of the trench are first lined with nitride to permit the growth of the thick bottom oxide to, for example 1000 Å to 1400 Å and the nitride is subsequently removed and a thin oxide, for example 320 Å is regrown on the side walls. In another embodiment, the trench bottom in amorphized and the trench walls are left as single crystal silicon so that oxide can be grown much faster and thicker on the trench bottom than on the trench walls during an oxide growth step. A reduced channel length of about 0.7 microns is used. The source diffusion is made deeper than the implant damage depth so that the full 0.7 micron channel is along undamaged silicon.