Patents by Inventor Naresh U. Mehta

Naresh U. Mehta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Distributed test system and method
    Patent number: 8005638
    Abstract: Provided is a distributed test system and method for electrical devices that features bifurcated testing and analysis of test results for electrical devices by aggregating test results from multiple testing systems to a centralized server where analysis of test data is undertaken. The system includes a plurality of testing systems, each of which is configured to operate test software to provide electrical stimuli to devices under test (DUTs) and obtain measured metrics indicative of actual operational characteristics (AOCs) of the DUTs. A decision support system (DSS) is selectively placed in data communication with the plurality of testing systems to receive the measured metrics from each of the plurality of testing systems. The DSS is configured to operate on software and compare desired metrics, indicative of desired operational characteristics (DOCs) of each of the DUTs, with the measured metrics and provide a plurality of operational characteristic determinations (OCDs).
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: August 23, 2011
    Assignee: Altera Corporation
    Inventors: Naresh U. Mehta, Parmeshwar Roddy Bayappu
  • Method and device for test vector analysis
    Patent number: 6197605
    Abstract: A method and device for testing and manufacturing integrated circuits such as microprocessors, memories, ASICs, programmable logic, and other types of integrated circuits. A test system is designed to test the relevant integrated circuit. A device under test emulator responds to the test system. If modifications are needed, the test system can be modified, and used to test actual devices.
    Type: Grant
    Filed: May 27, 1999
    Date of Patent: March 6, 2001
    Assignee: Altera Corporation
    Inventors: Tajana Simunic, Naresh U. Mehta, Caleb Crome
  • Method and device for test vector analysis
    Patent number: 5923567
    Abstract: A method and device for testing and manufacturing integrated circuits such as microprocessors, memories, ASICs, programmable logic, and other types of integrated circuits. A test system is designed to test the relevant integrated circuit. A device under test emulator responds to the test system. If modifications are needed, the test system can be modified, and used to test actual devices.
    Type: Grant
    Filed: October 9, 1996
    Date of Patent: July 13, 1999
    Assignee: Altera Corporation
    Inventors: Tajana Simunic, Naresh U. Mehta, Caleb Crome
  • System and method for performing database query using a marker table
    Patent number: 5893088
    Abstract: A system and method for performing complex queries in a database system. The method identifies a single type of entity in the database. A table or set of columns is formed that is used to track which entries meet the various subcriteria in a complex query through entry of binary marker bits. Logical operations may be performed on such marker bits to identify those entities meeting the specified search criteria. Through appropriate search planning, the bits may be "reused" during the query search. The method may be used in combination with, for example, index searches and other optimized searching techniques.
    Type: Grant
    Filed: September 19, 1996
    Date of Patent: April 6, 1999
    Assignee: Altera Corporation
    Inventors: Matthew C. Hendricks, Kirk R. Martinez, Naresh U. Mehta