Patents by Inventor Nariaki YAMAMOTO

Nariaki YAMAMOTO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230397700
    Abstract: Through-holes are formed at a constant pitch along a side-edge portion of a fastener tape where a tape base fabric is covered by a waterproof layer, the through-holes piercing the fastener tape. Plasma treatment or corona treatment is applied to the side-edge portion of the fastener tape so as to form an activation region on a surface of the waterproof layer on one or both sides of the fastener tape. Injection molding of fastener elements is performed to attach the fastener elements to the side-edge portion of the fastener tape. Melted resin adheres to the activation region and fills the through-hole before solidifying into the fastener element.
    Type: Application
    Filed: October 22, 2020
    Publication date: December 14, 2023
    Inventors: Yuki SAKAGAMI, Mineto TERADA, Nariaki YAMAMOTO, Steven THOMAS, Mark BRADY
  • Patent number: 8508585
    Abstract: A three-dimensional video reproduction apparatus includes: a video decoder unit which generates a right-eye video signal and a left-eye video signal; a graphics decoder unit which generates a right-eye graphics signal and a left-eye graphics signal; a synthesizing unit which synthesizes the right-eye video signal and the right-eye graphics signal and synthesizes the left-eye video signal and the left-eye graphics signal, to generate a right-eye output signal and a left-eye output signal; and an output unit which reproduces the three-dimensional video by alternately outputting the right-eye and left-eye output signals. When two adjacent pixels in the right-eye or left-eye output signal are represented by a common chrominance signal, and are generated respectively using a video signal and a graphics signal, the synthesizing unit generates the common chrominance signal such that a synthesis ratio of the video signal and the graphics signal is biased in favor of one of these.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: August 13, 2013
    Assignee: Panasonic Corporation
    Inventors: Nariaki Yamamoto, Akira Matsubara
  • Publication number: 20110228060
    Abstract: A three-dimensional video reproduction apparatus includes: a video decoder unit which generates a right-eye video signal and a left-eye video signal; a graphics decoder unit which generates a right-eye graphics signal and a left-eye graphics signal; a synthesizing unit which synthesizes the right-eye video signal and the right-eye graphics signal and synthesizes the left-eye video signal and the left-eye graphics signal, to generate a right-eye output signal and a left-eye output signal; and an output unit which reproduces the three-dimensional video by alternately outputting the right-eye and left-eye output signals. When two adjacent pixels in the right-eye or left-eye output signal are represented by a common chrominance signal, and are generated respectively using a video signal and a graphics signal, the synthesizing unit generates the common chrominance signal such that a synthesis ratio of the video signal and the graphics signal is biased in favor of one of these.
    Type: Application
    Filed: March 17, 2011
    Publication date: September 22, 2011
    Inventors: Nariaki YAMAMOTO, Akira Matsubara
  • Publication number: 20110032422
    Abstract: In a video processing system which divides HD-size image data into a plurality pieces of sub-image data and performs image processing for upconversion to 4K×2K image data, four image processors synchronous with an HD signal each process a corresponding one of the four pieces of sub-image data. In this case, the image processors process the four pieces of sub-image regions while causing the four pieces of sub-image regions to overlap at their division boundaries, and particularly process the overlapping regions during respective blanking periods. After the image processing of the image processors, the overlapping data is removed. Thereafter, the pieces of image data of the four sub-regions are combined. Therefore, the division boundaries of the pieces of sub-images can be processed without a degradation in image quality.
    Type: Application
    Filed: October 18, 2010
    Publication date: February 10, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Nariaki YAMAMOTO, Shun KINOSHITA, Hiroshi TANIUCHI, Kunihiro KAIDA, Kazuyuki ISHIDA
  • Publication number: 20090227373
    Abstract: The present invention is related to reducing difference between a period of time elapsing until a first moving object moving in conjunction with a motion of a first character passes through a plane and a period of time elapsing until a second moving object released by a second character passes through he plane. A first moving object moving in conjunction with a motion of a first character is displayed on an image display unit with image data for the first moving object. Then, arrival time elapsing since a second moving object is released by a second character until the second moving object arrives at a predicted passage plane is computed based on velocity of the second moving object and distance from a position of the second moving object when the first moving object starts performing a motion to the predicted passage plane. Next, a control unit executes processing of correcting base arrival time for reducing absolute value of difference between the base arrival time and the arrival time.
    Type: Application
    Filed: March 4, 2009
    Publication date: September 10, 2009
    Applicant: KONAMI DIGITAL ENTERTAINMENT CO., LTD.
    Inventor: Nariaki YAMAMOTO
  • Publication number: 20080211962
    Abstract: When it is detected that a write address signal and a read address signal coincide with each other during in the judgment range state, an address value of the write address signal is held to halt writing into a memory, whereby a video signal is outputted without mixing old and new frames therein. Therefore, a buffer area in the memory can be minimized, and an address control circuit can be appropriately controlled even when the frame frequency difference exceed a buffer capacity, thereby a frame synchronizer circuit that can output normal pictures is provided.
    Type: Application
    Filed: December 19, 2007
    Publication date: September 4, 2008
    Inventors: Hisaji Murata, Toshihiro Miyoshi, Nariaki Yamamoto