Patents by Inventor Narikazu Usuki

Narikazu Usuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device and method for testing same
    Patent number: 7142472
    Abstract: A semiconductor memory device having a sense amplifier for detecting data stored in a memory cell via a bit line pair connected to the memory cell, and voltage application means, an output voltage of which being adjustable, for applying the output voltage to the bit line pair so as to disturb potentials on the bit line pair.
    Type: Grant
    Filed: October 6, 2004
    Date of Patent: November 28, 2006
    Assignee: Elpida Memory, Inc.
    Inventor: Narikazu Usuki
  • Semiconductor memory device and method for testing same
    Publication number: 20050073891
    Abstract: A semiconductor memory device having a sense amplifier for detecting data stored in a memory cell via a bit line pair connected to the memory cell, and voltage application means, an output voltage of which being adjustable, for applying the output voltage to the bit line pair so as to disturb potentials on the bit line pair.
    Type: Application
    Filed: October 6, 2004
    Publication date: April 7, 2005
    Inventor: Narikazu Usuki
  • Semiconductor memory device with less data transfer delay time
    Patent number: 6687181
    Abstract: In a semiconductor memory device, a memory cell array has an even bank activated based on even numbered addresses and an odd bank activated based on odd numbered addresses. Even read data is outputted from the even bank in response to a first control signal, and odd read data is outputted from the odd bank in response to the first read control signal. A relaying unit receives the even read data on the first even data bus to output the even read data to the second even data bus in response to a second read control signal, and receives the odd read data on the first odd data bus to output the odd read data to the second odd data bus in response to the second read control signal. An I/O circuit receives the even read data from the second even data bus and the odd read data from the second odd data bus, and outputs one of the even read data and the odd read data to the common data bus and then outputs the other to the common data bus, in response to a third read control signal.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: February 3, 2004
    Assignees: NEC Corporation, Hitachi, Ltd., NEC Electronics Corporation
    Inventors: Narikazu Usuki, Kanji Oishi
  • Semiconductor memory device with less data transfer delay time
    Publication number: 20030043682
    Abstract: In a semiconductor memory device, a memory cell array has an even bank activated based on even numbered addresses and an odd bank activated based on odd numbered addresses. Even read data is outputted from the even bank in response to a first control signal, and odd read data is outputted from the odd bank in response to the first read control signal. A relaying unit receives the even read data on the first even data bus to output the even read data to the second even data bus in response to a second read control signal, and receives the odd read data on the first odd data bus to output the odd read data to the second odd data bus in response to the second read control signal. An I/O circuit receives the even read data from the second even data bus and the odd read data from the second odd data bus, and outputs one of the even read data and the odd read data to the common data bus and then outputs the other to the common data bus, in response to a third read control signal.
    Type: Application
    Filed: August 28, 2002
    Publication date: March 6, 2003
    Applicant: NEC CORPORATION
    Inventors: Narikazu Usuki, Kanji Oishi