Abstract: A microprocessor for enhancing the initiation of data processing after execution of a conditional branch instruction, by decoding a branch target instruction immediately when a branch is taken. An instruction prefetch cycle for a branch target instruction is initiated before the execution of a conditional branch is completed and by utilizing the branch address the byte data to be outputted from a branch buffer is selected and transferred to the instruction decoder.

Abstract: A microprocessor which prefetches instructions in words which contain a fixed plurality of bytes based on addresses which disregard one or more less significant bits and in which instructions comprises a variable number of bytes includes an adder for supplying information regarding the starting location for each instruction within a multi-byte, prefetched word held in a queue for alignment of the instruction for decoding by an instruction decoder. Upon the occurrence of an unconditional branch instruction or a conditional branch instruction in which the condition is met, a multiplexer is used to substitute a starting location stored in a branch hit table for the branch target instruction within a multi-byte, prefetched word for the starting for the starting location developed by the adder.

Abstract: A microprocessor having the instruction decoding operation performed by a precoder unit and a main decoder unit which operates in a pipelined manner by providing a buffer for temporarily storing information from the precoder unit positioned between the precoder unit and the main decoder unit. The microprocessor supports different instruction formats and operand addressing modes without lowering the instruction decoding speed.

Abstract: An improved microprocessor in which distribance of a pipeline processing flow caused by a conditional branch instruction is suppressed. The microprocessor includes an instruction decoder unit having a precedent decoding function in which at least one instruction subsequent to a conditional branch instruction or an instruction at a branch destination address is decoded in advance during a branch condition unsettled period. A register queue temporarily stores the decoded instructions and a mask control unit responds to the decoder unit by masking a ready state for execution of at least one decoded instruction.

Abstract: A sequence controller for designating an operating state to be performed currently, includes a set of terminals from which first data for designating a current operating state is derived, a state designation circuit producing second data for designating a next operating state in response to said first data, a latch circuit coupled between the state designation circuit and the set of terminals for latching and outputting the second data instead of the first data in response to a strobe signal, and a signal generator supplied with a clock signal for producing the strobe signal in synchronism with the clock signal when a response signal to the current operating state is returned to the controller.