Abstract: A high frequency clock signal synthesizer circuit employs a single fixed reference clock signal to generate one or more variable frequency clock signals. A phase comparator and a variable count counter generate a control signal from the reference clock and circuit output and provide it to a voltage controlled oscillator. High frequency stability of the voltage controlled oscillator is provided by a ring oscillator with a control signal response which is linear even at high frequencies. The ring oscillator employs an odd number of inverting delay stages coupled in series in a ring configuration, each delay stage having an input, an output, an inverter coupled to the input and a controllable current source buffering the switching transistors of the inverter from the output. A bias circuit controls the current of the current source and thereby controls the delay of each delay stage and thus the frequency of the ring oscillator.