Patents by Inventor Narsing K. Vijayrao

Narsing K. Vijayrao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8606999
    Abstract: A method and apparatus for partitioning a cache includes determining an allocation of a subcache out of a plurality of subcaches within the cache for association with a compute unit out of a plurality of compute units. Data is processed by the compute unit, and the compute unit evicts a line. The evicted line is written to the subcache associated with the compute unit.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: December 10, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Greggory D. Donley, William Alexander Hughes, Narsing K. Vijayrao
  • Publication number: 20120042127
    Abstract: A method and apparatus for partitioning a cache includes determining an allocation of a subcache out of a plurality of subcaches within the cache for association with a compute unit out of a plurality of compute units. Data is processed by the compute unit, and the compute unit evicts a line. The evicted line is written to the subcache associated with the compute unit.
    Type: Application
    Filed: August 30, 2010
    Publication date: February 16, 2012
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Greggory D. Donley, William Alexander Hughes, Narsing K. Vijayrao
  • Patent number: 6820106
    Abstract: A method and apparatus to increase the performance of a floating point multiplier accumulator (FMAC). The method comprises receiving three floating point numbers and computing a product of the first floating point number and the second floating point number and adding a third floating point number to produce a sum value and a carry value. A propagate value, a kill value and a generate value are then computed based on the sum value and the carry value. Simultaneously the sum value is added to the carry value to create a first result, the sum value is added to the carry value and incremented by one to create a second result, the sum value is added to the carry value and incremented by two to create a third result, and a decimal point position is determined. One of the first result, the second result and the third result is then selected responsive to a rounding mode and the decimal point position. The selected result is normalized based on the decimal point position.
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: November 16, 2004
    Assignee: Intel Corporation
    Inventors: Narsing K. Vijayrao, Chi Keung Lee, Sudarshan Kumar
  • Publication number: 20030208686
    Abstract: A method of protecting data received on a client device while coupled to a network through a communication channel has been disclosed. A client device (130) may receive protected data through a communication channel (140). A user public key (320) and a user private key (410) may be received by the client device (130). When protected data is to be stored on permanent storage (640), a link to a hidden file (220) may be generated using a random number generator. The link may be encrypted using user public key (320) to generate an encrypted link. Protected data may be stored in hidden file (220) and the encrypted link may be stored in a shield file (210). When the protected data is read from permanent storage (640), the encrypted link may be decrypted using user private key (410) to generate the link identifying hidden file (220). User private key (410) may not be stored on permanent storage (640).
    Type: Application
    Filed: May 6, 2002
    Publication date: November 6, 2003
    Inventors: Damodar R. Thummalapally, Narsing K. Vijayrao
  • Patent number: 6111435
    Abstract: A circuit includes first and second pull-up transistors having first and second drains, respectively, each coupled to separate voltage clamps. The gates of each of the two pull-up transistors are coupled to a clock signal line. The circuit further includes a shared pull-down transistor, the gate of which is coupled to the clock signal line. The drain of the shared pull-down transistor is coupled to the first drain via at least one pull-down transistor in series with the shared pull-down transistor. The drain of the shared pull-down transistor is also coupled to the second drain via at least one pull-down transistor in series with the shared pull-down transistor. This circuit may be found useful in multiplexing applications.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: August 29, 2000
    Assignee: Intel Corporation
    Inventors: Jiann-Cherng James Lan, Mahadevamurty Nemani, Narsing K. Vijayrao, Wenjie Jiang, Sudarshan Kumar
  • Patent number: 6058403
    Abstract: A broken stack domino priority encoder to provide a set of voltages to uniquely identify the position of a leading one or leading zero in a binary word, the domino priority encoder comprising a by-pass stack of nMOSFETs and a broken stack of nMOSFETs to discharge various nodes. The stack depth of nMOSFETs between each node and ground is minimized in order to maximize switching speed of the priority encoder.
    Type: Grant
    Filed: August 6, 1998
    Date of Patent: May 2, 2000
    Assignee: Intel Corporation
    Inventors: Narsing K. Vijayrao, Sudarshan Kumar