Abstract: A system and method for multi-channel communication with dual in-line memory modules (“DIMMs”) is disclosed. The system retrieves information characterizing a plurality of memory channels, each of each is configurable to facilitate data communication between a DIMM and a memory controller with associated memory channel interfaces. Based on the retrieved information, one of the memory channels is designated as the active memory channel, granting the designated memory channel the ability to issue memory requests or transactions to the DIMM. On a periodic or as-needed basis (e.g., when the active memory channel is stalled or nearly stalled), the system determines whether to designate a different of the memory channels as the active memory channel, thereby enabling the newly-designated active memory channel the ability to issue memory requests or transactions to the DIMM. In some embodiments, only one of the memory channels is active at a time for communication with each DIMM.

Abstract: Technology is provided for partitioning a shared unified cache in a multi-processor computer system. The technology can receive a request to allocate a portion of a shared unified cache memory for storing only executable instructions, partition the cache memory into multiple partitions, and allocate one of the partitions for storing only executable instructions. The technology can further determine the size of the portion of the cache memory to be allocated for storing only executable instructions as a function of the size of the multi-processor's L1 instruction cache and the number of cores in the multi-processor.

Abstract: A system and method for multi-channel communication with dual in-line memory modules (“DIMMs”) is disclosed. The system retrieves information characterizing a plurality of memory channels, each of each is configurable to facilitate data communication between a DIMM and a memory controller with associated memory channel interfaces. Based on the retrieved information, one of the memory channels is designated as the active memory channel, granting the designated memory channel the ability to issue memory requests or transactions to the DIMM. On a periodic or as-needed basis (e.g., when the active memory channel is stalled or nearly stalled), the system determines whether to designate a different of the memory channels as the active memory channel, thereby enabling the newly-designated active memory channel the ability to issue memory requests or transactions to the DIMM. In some embodiments, only one of the memory channels is active at a time for communication with each DIMM.

Abstract: Some embodiments of this disclosure operate a network device in conjunction with a social networking system. The operations can include establishing a network island by providing network connectivity in a local region via the network device; connecting the network device to an intermittent network channel that is not continuously active; when the intermittent network channel is active, receiving a content item via the intermittent network channel, wherein the content items is not destined for a specific device in the network island; and caching the content item in a cache storage of the network device such that the content item is available to be accessed by any computing device within the network island.

Abstract: A method of operating a data transport system on a computing device is disclosed. The method comprises: writing outgoing data in a first memory space on a memory module of a computing device; detecting the outgoing data on the first memory space by a data channel component coupled to the memory module, wherein the first memory space is designated for external data transmission; and generating a transmission signal encoding the outgoing data, via the data channel component, for transmission from the memory module through an inter-device interconnect to an external memory module.

Abstract: A computing device has a motherboard, at least two daughter boards communicably connected to the motherboard, each of the at least two daughter boards having at least a specialized processor and a high-speed inter-processor communications port; and at least two high-speed inter-processor communication interconnects connecting at least two of the high-speed inter-processor communications ports. The configuration enables a flexible topology architecture, e.g., for different applications, and rapid reuse of system components even when new specialized processors become available.

Abstract: Embodiments are disclosed for managing a distributed data center. The managing can include receiving content interaction history associated with a first social networking account of a social networking system at a content distribution system; maintaining a cache map of available cache appliances to implement a distributed cache store; selecting a content item to push to a residential cache appliance based on the content interaction history, wherein pushing the content item includes updating the cache map to associate a network address of the residential cache appliance with an identifier of the content item; and providing a content distribution service configured to redirect a content streaming request for the content item to the residential cache appliance when the content item is determined to be available in the distributed cache store according to the cache map.

Abstract: Systems and methods for optical communication using single source optical transmission are disclosed. A representative method includes receiving optical signals at a first frequency by a receiver (RX) from an optical fiber. The received optical signals are routed to a modulator that modulates the optical signals at a second frequency. The optical signals are emitted by a transmitter (TX) back to the optical fiber at the second frequency.

Abstract: A computing device has a motherboard, at least two daughter boards communicably connected to the motherboard, each of the at least two daughter boards having at least a specialized processor and a high-speed inter-processor communications port; and at least two high-speed inter-processor communication interconnects connecting at least two of the high-speed inter-processor communications ports. The configuration enables a flexible topology architecture, e.g., for different applications, and rapid reuse of system components even when new specialized processors become available.

Abstract: Optical communication using optical resonators with noise margins is disclosed. A representative system includes an optical fiber for transmitting optical signals, a receiver configured to receive the optical signals, and a plurality of optical resonators optically connecting the optical fiber to the receiver. The individual optical resonators can have peak sensitivities at mutually different wavelengths of light. In some embodiments the optical resonators can be Q-switches.

Abstract: The present disclosure relates to a home automation system that is automated based on user preferences provided by a social networking system, where the home automation system provides a short-range, high-speed wireless connection that is contained within the safe boundaries of a home. Briefly described, the home automation system employs one or more home automation devices to control various home devices within the home based on detection of one or more users' social profile, where each home automation device is configured to broadcast and communicate via a short-range, multi-gigabit-per-second (MGbps) wireless communication link that can be utilized by the various home devices. Furthermore, each home automation device is configured to be self-tuning, thereby enabling automatic efficient management of the MGbps wireless communication link.

Abstract: A system and method for multi-channel communication with dual in-line memory modules (“DIMMs”) is disclosed. The system retrieves information characterizing a plurality of memory channels, each of each is configurable to facilitate data communication between a DIMM and a memory controller with associated memory channel interfaces. Based on the retrieved information, one of the memory channels is designated as the active memory channel, granting the designated memory channel the ability to issue memory requests or transactions to the DIMM. On a periodic or as-needed basis (e.g., when the active memory channel is stalled or nearly stalled), the system determines whether to designate a different of the memory channels as the active memory channel, thereby enabling the newly-designated active memory channel the ability to issue memory requests or transactions to the DIMM. In some embodiments, only one of the memory channels is active at a time for communication with each DIMM.

Abstract: The disclosure is directed to a cache management system (“system”) for storing data in a cache of a computer system in a compact form. The system identifies multiple instances of a candidate value stored in a primary cache and stores those instances as a single value in a value cache. The system stores multiple pointers to the candidate value in the value cache, e.g., as many as the number of occurrences of the candidate value in the primary cache, each of which corresponds to an address in a memory of the computer system storing an instance of the primary cache candidate value. By storing multiple instances of the candidate value as a single instance, the system reduces the cache pollution and the memory bandwidth and facilitates storing more number of distinct values in the primary cache of a given size.

Abstract: The disclosure is directed to a cache management system (“system”) for storing data in a cache of a computer system in a compact form. The system identifies multiple instances of a candidate value stored in a primary cache and stores those instances as a single value in a value cache. The system stores multiple pointers to the candidate value in the value cache, e.g., as many as the number of occurrences of the candidate value in the primary cache, each of which corresponds to an address in a memory of the computer system storing an instance of the primary cache candidate value. By storing multiple instances of the candidate value as a single instance, the system reduces the cache pollution and the memory bandwidth and facilitates storing more number of distinct values in the primary cache of a given size.

Abstract: Various embodiments (“systems”) are described for transferring data from a primary storage (e.g., magnetic disk drives, solid state drives, etc.) to an optical cold storage rack. The optical cold storage rack may include many physical optical storage disks, but a much smaller number of burners and readers (e.g., optical disk drives). When data is to be transferred to the optical cold storage rack, the system may generate a plan for performing the transfer. “Migration worker” components may then implement the plan and may be exclusively dedicated to implementing such plans. In various embodiments, the plan may specify how large data file “aggregates” (collections of portions of one or more data files) are to be distributed across optical disks (“disks”) to improve throughput during subsequent reading operations from the optical cold storage rack. The plan may also anticipate the relation between the limited number of burners/readers and the overall optical cold storage rack disk capacity.

Abstract: The disclosure is directed to storing data in different tiers of a database based on the access pattern of the data. Immutable data, e.g., data that does not change or changes less often than a specified threshold, is stored in a first storage tier of the database, and mutable data, e.g., data that changes more often than immutable data, is stored in a second storage tier of the database. The second storage tier of the database is more performant than the first storage tier, e.g., the second storage tier has a higher write endurance and a lower write latency than the first storage tier. All writes to the database are performed at the second storage tier and reads on both storage tiers. The storage tiers are synchronized, e.g., the set of data is copied from the second to the first storage tier based on a trigger, e.g., a specified schedule.

Abstract: Technology is provided for partitioning a shared unified cache in a multi-processor computer system. The technology can receive a request to allocate a portion of a shared unified cache memory for storing only executable instructions, partition the cache memory into multiple partitions, and allocate one of the partitions for storing only executable instructions. The technology can further determine the size of the portion of the cache memory to be allocated for storing only executable instructions as a function of the size of the multi-processor's L1 instruction cache and the number of cores in the multi-processor.

Abstract: Systems and methods for optical communication using single source optical transmission are disclosed. A representative method includes receiving optical signals at a first frequency by a receiver (RX) from an optical fiber. The received optical signals are routed to a modulator that modulates the optical signals at a second frequency. The optical signals are emitted by a transmitter (TX) back to the optical fiber at the second frequency.

Abstract: Optical communication using optical resonators with noise margins is disclosed. A representative system includes an optical fiber for transmitting optical signals, a receiver configured to receive the optical signals, and a plurality of optical resonators optically connecting the optical fiber to the receiver. The individual optical resonators can have peak sensitivities at mutually different wavelengths of light. In some embodiments the optical resonators can be Q-switches.

Abstract: Technology is provided for partitioning a shared unified cache in a multi-processor computer system. The technology can receive a request to allocate a portion of a shared unified cache memory for storing only executable instructions, partition the cache memory into multiple partitions, and allocate one of the partitions for storing only executable instructions. The technology can further determine the size of the portion of the cache memory to be allocated for storing only executable instructions as a function of the size of the multi-processor's L1 instruction cache and the number of cores in the multi-processor.