Patents by Inventor Naruhisa Miura

Naruhisa Miura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10510843
    Abstract: An insulated gate silicon carbide semiconductor device includes: a drift layer of a first conductivity type on a silicon carbide substrate of 4H type with a {0001} plane having an off-angle of more than 0° as a main surface; a first base region; a source region; a trench; a gate insulating film; a protective diffusion layer; and a second base region. The trench sidewall surface in contact with the second base region is a surface having a trench off-angle of more than 0° in a <0001> direction with respect to a plane parallel to the <0001> direction. The insulated gate silicon carbide semiconductor device can relieve an electric field of a gate insulating film and suppress an increase in on-resistance and provide a method for manufacturing the same.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: December 17, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yasuhiro Kagawa, Rina Tanaka, Yutaka Fukui, Naruhisa Miura, Yuji Abe, Masayuki Imaizumi
  • Publication number: 20190355821
    Abstract: A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.
    Type: Application
    Filed: July 30, 2019
    Publication date: November 21, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yukiyasu NAKAO, Masayuki IMAIZUMI, Shuhei NAKATA, Naruhisa MIURA
  • Patent number: 10418444
    Abstract: A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: September 17, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yukiyasu Nakao, Masayuki Imaizumi, Shuhei Nakata, Naruhisa Miura
  • Patent number: 10347724
    Abstract: A gate insulating film covers a trench penetrating through a source region and a body region and reaching a drift layer in each of a first cell region and a second cell region. The gate electrode is provided in the trench. A high-concentration layer of the first conductivity type is provided between the drift layer and the body region in the first cell region and has a second impurity concentration higher than the first impurity concentration. A current restriction layer is provided between the drift layer and the body region in the second cell region and has the first conductivity type and a third impurity concentration higher than the first impurity concentration and lower than the second impurity concentration.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: July 9, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Rina Tanaka, Katsutoshi Sugawara, Yasuhiro Kagawa, Naruhisa Miura
  • Patent number: 10157986
    Abstract: A drift layer of a first conductivity type is made of silicon carbide. A body region of a second conductivity type is provided on the drift layer. A source region of the first conductivity type is provided on the body region. A source electrode is connected to the source region. A gate insulating film is provided on side and bottom surfaces of a trench which penetrates the body region and the source region. A gate electrode is provided in the trench with the gate insulating film interposed therebetween. A trench-bottom-surface protective layer of the second conductivity type provided below the bottom surface of the trench in the drift layer is electrically connected to the source electrode. The trench-bottom-surface protective layer has a high-concentration protective layer, and a first low-concentration protective layer provided below the high-concentration protective layer and having an impurity concentration lower than that of the high-concentration protective layer.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: December 18, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Rina Tanaka, Yasuhiro Kagawa, Katsutoshi Sugawara, Naruhisa Miura
  • Publication number: 20180315819
    Abstract: A gate insulating film covers a trench penetrating through a source region and a body region and reaching a drift layer in each of a first cell region and a second cell region. The gate electrode is provided in the trench. A high-concentration layer of the first conductivity type is provided between the drift layer and the body region in the first cell region and has a second impurity concentration higher than the first impurity concentration. A current restriction layer is provided between the drift layer and the body region in the second cell region and has the first conductivity type and a third impurity concentration higher than the first impurity concentration and lower than the second impurity concentration.
    Type: Application
    Filed: December 7, 2015
    Publication date: November 1, 2018
    Applicant: Mitsubishi Electric Corporation
    Inventors: Rina TANAKA, Katsutoshi SUGAWARA, Yasuhiro KAGAWA, Naruhisa MIURA
  • Patent number: 10062758
    Abstract: A semiconductor device having a low feedback capacitance and a low switching loss. The semiconductor device includes: a substrate; a drift layer formed on a surface of the semiconductor substrate; a plurality of first well regions formed on a surface of the drift layer; a source region which is an area formed on a surface of each of the first well regions and defining, as a channel region, the surface of each of the first well regions interposed between the area and the drift layer; a gate electrode formed over the channel region and the drift layer thereacross through a gate insulating film; and second well regions buried inside the drift layer below the gate electrode and formed to be individually connected to each of the first well regions adjacent to one another.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: August 28, 2018
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Hiroshi Watanabe
  • Patent number: 10002931
    Abstract: A silicon carbide semiconductor device capable of effectively increasing a threshold voltage and a method for manufacturing the silicon carbide semiconductor device. The silicon carbide semiconductor device includes a gate insulating film formed on part of surfaces of the well regions and the source region; and a gate electrode formed on a surface of the gate insulating film so as to be opposite to an end portion of the source region and the well regions. Furthermore, the gate insulating film has, in an interface region between the well regions and the gate insulating film, defects that each form a first trap having an energy level deeper than a conduction band end of silicon carbide and that include a bond between silicon and hydrogen.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: June 19, 2018
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Masayuki Furuhashi, Naruhisa Miura
  • Patent number: 9972676
    Abstract: A silicon carbide semiconductor device includes: a drift layer of a first conductivity type made of silicon carbide; a well region of a second conductivity type formed on the drift layer; a source region of a first conductivity type formed on the well region; a gate insulating film formed on an inner wall of a trench extending from a front surface of the source region through the well region, at least a part of a side surface of the gate insulating film being in contact with the drift layer; a gate electrode formed in the trench with the gate insulating film therebetween; a protective layer of the second conductivity type formed in the drift layer; and a depletion suppressing layer of the first conductivity type formed in the drift layer so as to be in contact with a side surface of the protective layer.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: May 15, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Rina Tanaka, Yasuhiro Kagawa, Naruhisa Miura, Yuji Ebiike
  • Patent number: 9954072
    Abstract: A silicon-carbide semiconductor device that relaxes field intensity in a gate insulating film, and that has a low ON-resistance. The silicon-carbide semiconductor device includes: an n-type silicon-carbide substrate; a drift layer formed on a topside of the n-type silicon-carbide substrate; a trench formed in the drift layer and that includes therein a gate insulating film and a gate electrode; a p-type high-concentration well region formed parallel to the trench with a spacing therefrom and that has a depth larger than that of the trench; and a p-type body region formed to have a depth that gradually increases when nearing from a position upward from the bottom end of the trench by approximately the thickness of the gate insulating film at the bottom of the trench toward the lower end of the p-type high-concentration well region.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: April 24, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Rina Tanaka, Yasuhiro Kagawa, Shiro Hino, Naruhisa Miura, Masayuki Imaizumi
  • Publication number: 20180076285
    Abstract: A drift layer of a first conductivity type is made of silicon carbide. A body region of a second conductivity type is provided on the drift layer. A source region of the first conductivity type is provided on the body region. A source electrode is connected to the source region. A gate insulating film is provided on side and bottom surfaces of a trench which penetrates the body region and the source region. A gate electrode is provided in the trench with the gate insulating film interposed therebetween. A trench-bottom-surface protective layer of the second conductivity type provided below the bottom surface of the trench in the drift layer is electrically connected to the source electrode. The trench-bottom-surface protective layer has a high-concentration protective layer, and a first low-concentration protective layer provided below the high-concentration protective layer and having an impurity concentration lower than that of the high-concentration protective layer.
    Type: Application
    Filed: November 19, 2015
    Publication date: March 15, 2018
    Applicant: Mitsubishi Electric Corporation
    Inventors: Rina TANAKA, Yasuhiro KAGAWA, Katsutoshi SUGAWARA, Naruhisa MIURA
  • Patent number: 9825126
    Abstract: A source region of a MOSFET includes a source contact region connected to a source electrode, a source extension region adjacent to a channel region of a well region, and a source resistance control region provided between the source extension region and the source contact region. The source resistance control region includes a low concentration source resistance control region which has an impurity concentration lower than that of the source contact region or the source extension region and a high concentration source resistance control region which is formed between the well region and the low concentration source resistance control region and has an impurity concentration higher than that of the low concentration source resistance control region.
    Type: Grant
    Filed: September 7, 2015
    Date of Patent: November 21, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hideyuki Hatta, Naruhisa Miura
  • Publication number: 20170309711
    Abstract: An insulated gate silicon carbide semiconductor device includes: a drift layer of a first conductivity type on a silicon carbide substrate of 4H type with a {0001} plane having an off-angle of more than 0° as a main surface; a first base region; a source region; a trench; a gate insulating film; a protective diffusion layer; and a second base region. The trench sidewall surface in contact with the second base region is a surface having a trench off-angle of more than 0° in a <0001> direction with respect to a plane parallel to the <0001> direction. The insulated gate silicon carbide semiconductor device can relieve an electric field of a gate insulating film and suppress an increase in on-resistance and provide a method for manufacturing the same.
    Type: Application
    Filed: July 11, 2017
    Publication date: October 26, 2017
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yasuhiro KAGAWA, Rina TANAKA, Yutaka FUKUI, Naruhisa MIURA, Yuji ABE, Masayuki IMAIZUMI
  • Patent number: 9741797
    Abstract: An insulated gate silicon carbide semiconductor device includes: a drift layer of a first conductivity type on a silicon carbide substrate of 4H type with a {0001} plane having an off-angle of more than 0° as a main surface; a first base region; a source region; a trench; a gate insulating film; a protective diffusion layer; and a second base region. The trench sidewall surface in contact with the second base region is a surface having a trench off-angle of more than 0° in a <0001> direction with respect to a plane parallel to the <0001> direction. The insulated gate silicon carbide semiconductor device can relieve an electric field of a gate insulating film and suppress an increase in on-resistance and provide a method for manufacturing the same.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: August 22, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yasuhiro Kagawa, Rina Tanaka, Yutaka Fukui, Naruhisa Miura, Yuji Abe, Masayuki Imaizumi
  • Publication number: 20170229535
    Abstract: A source region of a MOSFET includes a source contact region connected to a source electrode, a source extension region adjacent to a channel region of a well region, and a source resistance control region provided between the source extension region and the source contact region. The source resistance control region includes a low concentration source resistance control region which has an impurity concentration lower than that of the source contact region or the source extension region and a high concentration source resistance control region which is formed between the well region and the low concentration source resistance control region and has an impurity concentration higher than that of the low concentration source resistance control region.
    Type: Application
    Filed: September 7, 2015
    Publication date: August 10, 2017
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hideyuki HATTA, Naruhisa MIURA
  • Patent number: 9716006
    Abstract: A method for manufacturing a semiconductor device, includes: (a) providing a SiC epitaxial substrate in which on a SiC support substrate, a SiC epitaxial growth layer having an impurity concentration equal to or less than 1/10,000 of that of the SiC support substrate and having a thickness of 50 ?m or more is disposed; (b) forming an impurity region, which forms a semiconductor element, on a first main surface of the SiC epitaxial substrate by selectively injecting impurity ions; (c) forming an ion implantation region, which controls warpage of the SiC epitaxial substrate, on a second main surface of the SiC epitaxial substrate by injecting predetermined ions; and (d) heating the SiC epitaxial substrate after (b) and (c).
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: July 25, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenji Hamada, Naruhisa Miura, Yosuke Nakanishi
  • Patent number: 9704947
    Abstract: A semiconductor device including a terminal region that can suppress a resist collapse in manufacturing and effectively relieve a concentration of electric fields and a method for manufacturing the semiconductor device. The semiconductor device includes a semiconductor element formed in a semiconductor substrate made of a silicon carbide semiconductor of a first conductivity type and a plurality of ring-shaped regions of a second conductivity type formed in the semiconductor substrate while surrounding the semiconductor element in plan view. At least one of the plurality of ring-shaped regions includes one or more separation regions of the first conductivity type that cause areas of the first conductivity type on an inner side and an outer side of one of the ring-shaped regions to communicate with each other in plan view.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: July 11, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kohei Ebihara, Naruhisa Miura, Kenji Hamada, Koji Okuno
  • Publication number: 20170140934
    Abstract: A method for manufacturing a semiconductor device, includes: (a) providing a SiC epitaxial substrate in which on a SiC support substrate, a SiC epitaxial growth layer having an impurity concentration equal to or less than 1/10,000 of that of the SiC support substrate and having a thickness of 50 ?m or more is disposed; (b) forming an impurity region, which forms a semiconductor element, on a first main surface of the SiC epitaxial substrate by selectively injecting impurity ions; (c) forming an ion implantation region, which controls warpage of the SiC epitaxial substrate, on a second main surface of the SiC epitaxial substrate by injecting predetermined ions; and (d) heating the SiC epitaxial substrate after (b) and (c).
    Type: Application
    Filed: April 10, 2015
    Publication date: May 18, 2017
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kenji HAMADA, Naruhisa MIURA, Yosuke NAKANISHI
  • Patent number: 9640610
    Abstract: An IGBT includes an emitter electrode, base regions, an emitter region, a collector region, a collector electrode, a gate insulating film provided in contact with the silicon carbide semiconductor region, the emitter region, and the base region, and a gate electrode that faces the gate insulating film. A FWD includes a base contact region provided adjacent to the emitter region and electrically connected to the emitter electrode, and a cathode region disposed in the upper layer part on the other main surface side of the silicon carbide semiconductor region, provided adjacent to the collector region, and electrically connected to the collector electrode. The IGBT further includes a reduced carrier-trap region disposed in a principal current-carrying region of the silicon carbide semiconductor region located above the collector region and having a smaller number of carrier traps than the silicon carbide semiconductor region located above the cathode region.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: May 2, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenji Hamada, Naruhisa Miura
  • Patent number: 9577086
    Abstract: A device that increases a value of current flowing through a whole chip until a p-n diode in a unit cell close to a termination operates and reduces a size of the chip and a cost of the chip resulting from the reduced size. The device includes a second well region located to sandwich the entirety of a plurality of first well regions therein in plan view, a third separation region located to penetrate the second well region from a surface layer of the second well region in a depth direction, and a second Schottky electrode provided on the third separation region.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: February 21, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shiro Hino, Naruhisa Miura, Masayuki Imaizumi, Kohei Ebihara