Patents by Inventor Narula Bilik

Narula Bilik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230345723
    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier by conductive material of a lowest of the conductive tiers. Insulating material of the insulative tier that is immediately-directly above the lowest conductive tier is directly against a top of the conductive material of the lowest conductive tier. The insulating material comprises at least one of aluminum oxide, hafnium oxide, zirconium oxide, and carbon-doped insulative material. Other embodiments, including method, are disclosed.
    Type: Application
    Filed: April 25, 2022
    Publication date: October 26, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Yiping Wang, Adam W. Saxler, Narula Bilik
  • Patent number: 11700729
    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: July 11, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Yi Hu, Ramey M. Abdelrahaman, Narula Bilik, Daniel Billingsley, Zhenyu Bo, Joan M. Kash, Matthew J. King, Andrew Li, David Neumeyer, Wei Yeeng Ng, Yung K. Pak, Chandra Tiwari, Yiping Wang, Lance Williamson, Xiaosong Zhang
  • Patent number: 11569258
    Abstract: Some embodiments include a method of forming stacked memory decks. A first deck has first memory cells arranged in first tiers disposed one atop another, and has a first channel-material pillar extending through the first tiers. An inter-deck structure is over the first deck. The inter-deck structure includes an insulative expanse, and a region extending through the insulative expanse and directly over the first channel-material pillar. The region includes an etch-stop structure. A second deck is formed over the inter-deck structure. The second deck has second memory cells arranged in second tiers disposed one atop another. An opening is formed to extend through the second tiers and to the etch-stop structure. The opening is subsequently extended through the etch-stop structure. A second channel-material pillar is formed within the opening and is coupled to the first channel-material pillar. Some embodiments include integrated assemblies.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: January 31, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Liu Liu, David Daycock, Rithu K. Bhonsle, Giovanni Mazzone, Narula Bilik, Jordan D. Greenlee, Minsoo Lee, Benben Li
  • Publication number: 20220077169
    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.
    Type: Application
    Filed: November 12, 2021
    Publication date: March 10, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Yi Hu, Ramey M. Abdelrahaman, Narula Bilik, Daniel Billingsley, Zhenyu Bo, Joan M. Kash, Matthew J. King, Andrew Li, David Neumeyer, Wei Yeeng Ng, Yung K. Pak, Chandra Tiwari, Yiping Wang, Lance Williamson, Xiaosong Zhang
  • Patent number: 11205654
    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.
    Type: Grant
    Filed: August 25, 2019
    Date of Patent: December 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Yi Hu, Ramey M. Abdelrahaman, Narula Bilik, Daniel Billingsley, Zhenyu Bo, Joan M. Kash, Matthew J. King, Andrew Li, David Neumeyer, Wei Yeeng Ng, Yung K. Pak, Chandra Tiwari, Yiping Wang, Lance Williamson, Xiaosong Zhang
  • Publication number: 20210057428
    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.
    Type: Application
    Filed: August 25, 2019
    Publication date: February 25, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Yi Hu, Ramey M. Abdelrahaman, Narula Bilik, Daniel Billingsley, Zhenyu Bo, Joan M. Kash, Matthew J. King, Andrew Li, David Neumeyer, Wei Yeeng Ng, Yung K. Pak, Chandra Tiwari, Yiping Wang, Lance Williamson, Xiaosong Zhang
  • Publication number: 20200350333
    Abstract: Some embodiments include a method of forming stacked memory decks. A first deck has first memory cells arranged in first tiers disposed one atop another, and has a first channel-material pillar extending through the first tiers. An inter-deck structure is over the first deck. The inter-deck structure includes an insulative expanse, and a region extending through the insulative expanse and directly over the first channel-material pillar. The region includes an etch-stop structure. A second deck is formed over the inter-deck structure. The second deck has second memory cells arranged in second tiers disposed one atop another. An opening is formed to extend through the second tiers and to the etch-stop structure. The opening is subsequently extended through the etch-stop structure. A second channel-material pillar is formed within the opening and is coupled to the first channel-material pillar. Some embodiments include integrated assemblies.
    Type: Application
    Filed: July 20, 2020
    Publication date: November 5, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Liu Liu, David Daycock, Rithu K. Bhonsle, Giovanni Mazzone, Narula Bilik, Jordan D. Greenlee, Minsoo Lee, Benben Li
  • Patent number: 10748921
    Abstract: Some embodiments include a method of forming stacked memory decks. A first deck has first memory cells arranged in first tiers disposed one atop another, and has a first channel-material pillar extending through the first tiers. An inter-deck structure is over the first deck. The inter-deck structure includes an insulative expanse, and a region extending through the insulative expanse and directly over the first channel-material pillar. The region includes an etch-stop structure. A second deck is formed over the inter-deck structure. The second deck has second memory cells arranged in second tiers disposed one atop another. An opening is formed to extend through the second tiers and to the etch-stop structure. The opening is subsequently extended through the etch-stop structure. A second channel-material pillar is formed within the opening and is coupled to the first channel-material pillar. Some embodiments include integrated assemblies.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: August 18, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Liu Liu, David Daycock, Rithu K. Bhonsle, Giovanni Mazzone, Narula Bilik, Jordan D. Greenlee, Minsoo Lee, Benben Li
  • Publication number: 20200135751
    Abstract: Some embodiments include a method of forming stacked memory decks. A first deck has first memory cells arranged in first tiers disposed one atop another, and has a first channel-material pillar extending through the first tiers. An inter-deck structure is over the first deck. The inter-deck structure includes an insulative expanse, and a region extending through the insulative expanse and directly over the first channel-material pillar. The region includes an etch-stop structure. A second deck is formed over the inter-deck structure. The second deck has second memory cells arranged in second tiers disposed one atop another. An opening is formed to extend through the second tiers and to the etch-stop structure. The opening is subsequently extended through the etch-stop structure. A second channel-material pillar is formed within the opening and is coupled to the first channel-material pillar. Some embodiments include integrated assemblies.
    Type: Application
    Filed: October 25, 2018
    Publication date: April 30, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Liu Liu, David Daycock, Rithu K. Bhonsle, Giovanni Mazzone, Narula Bilik, Jordan D. Greenlee, Minsoo Lee, Benben Li